Semiconductor Science and Technology最新文献

A novel method to solve analytically the non-linear Poisson equation in the inversion layer of a MOSFET 分析解决 MOSFET 反相层非线性泊松方程的新方法

Semiconductor Science and Technology Pub Date : 2024-07-27 DOI: 10.1088/1361-6641/ad6837

Pedro Pereyra

{"title":"A novel method to solve analytically the non-linear Poisson equation in the inversion layer of a MOSFET","authors":"Pedro Pereyra","doi":"10.1088/1361-6641/ad6837","DOIUrl":"https://doi.org/10.1088/1361-6641/ad6837","url":null,"abstract":"\u0000 Despite the enormous importance that the metal oxide semiconductors (MOS) and the field effect transistors (MOSFETs) have in the actual semiconductor technology, the task of finding the analytical solution of the Poisson equation in the inversion layer was not fully accomplished for more than half a century. It is a well-known fact that due to the non-linear nature of this equation, the attempts to solve it got stuck after the first integration. Nevertheless, experimental and applied researchers found ways to characterize, control, and develop MOSFET devices based on approximate models, and numerical calculations. Here I present a new method to analytically solve the nonlinear Poisson equation, in principle, for any charge distribution in the inversion layer of a MOS, and for the charge density of the original Shockley model, in particular. To this purpose, a physical argument related to the charge and field energies in the transient population-inversion process is introduced and a new nonlinear {it but solvable} second order differential equation is obtained, whose solution also solves the original Poisson equation. The analytical results presented here allow us to derive explicit expressions for the electrical potential distribution and, very importantly, for the charge distribution, the inversion layer width and the effective impurity concentration in the depletion layer. The quantum Hall effect and other physical phenomena were discovered in the inversion layer of a MOS. The Hall effect was explained under the assumption that the charge distribution is a two-dimensional electron gas, we show here however that the 2D limit is reached only at high gate voltages. When applied to MOSFET structures, we obtain new expressions for the drain currents in the inversion and depletion layers, as functions of the impurity concentration and the gate voltage. This method can be used directly, as a building block, for multi-gate MOSFETs.","PeriodicalId":507064,"journal":{"name":"Semiconductor Science and Technology","volume":"6 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141797384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

MBE-grown ZnTe epitaxial layer based broadband photodetector with high response and excellent switching characteristics 基于 MBE 生长的 ZnTe 外延层的宽带光探测器，具有高响应和优异的开关特性

Semiconductor Science and Technology Pub Date : 2024-07-22 DOI: 10.1088/1361-6641/ad6636

Subodh Tyagi, Hardhyan Sheoran, Udai Ram Meena, Shivansh Tiwari, Puspashree Mishra, Shiv Kumar, Rajendra Singh

{"title":"MBE-grown ZnTe epitaxial layer based broadband photodetector with high response and excellent switching characteristics","authors":"Subodh Tyagi, Hardhyan Sheoran, Udai Ram Meena, Shivansh Tiwari, Puspashree Mishra, Shiv Kumar, Rajendra Singh","doi":"10.1088/1361-6641/ad6636","DOIUrl":"https://doi.org/10.1088/1361-6641/ad6636","url":null,"abstract":"\u0000 Zinc telluride (ZnTe) epitaxial layers were grown on gallium arsenide (GaAs) (211) substrate at different growth temperatures by molecular beam epitaxy (MBE). The fabricated interdigitated metal semiconductor metal (MSM) configuration-based photodetector on ZnTe epitaxial layers exhibited stable and excellent photo response in a broad spectral range (250 to 550 nm) up to 125 ℃. The room temperature and higher temperature (125 ℃) values of maximum current, spectral responsivity, and detectivity at an applied bias of 5 V and 550 nm wavelength were 3.5×10-8 A, 0.1 A/W and 1×1011 Jones and 1.7×10-6 A, 2.5 A/W and 1.5×1011 Jones, respectively. The maximum photo-to-dark-current ratio (PDCR) value at zero bias and 100 ℃ was obtained for the ZnTe layer grown at an optimum growth temperature of 380 ℃. The high PDCR value exhibits the self-powered capability of the detector. Further, the detector exhibits good On-Off switching to the illuminating light with rise and decay times less than 0.29 s and 0.4 s, respectively, at room temperature. The dependence of photo response on material quality was analysed by varying the substrate growth temperature. The broadband responsivity of the ZnTe-based photodetector shows its capability as a multicolour detector in UV and visible region with the use of suitable blocking filters.","PeriodicalId":507064,"journal":{"name":"Semiconductor Science and Technology","volume":"25 17","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141814517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Rare earth oxide Y2O3 modified g-C3N4 for efficient photocatalytic hydrogen production: Photocatalytic performance and electron transfer channels 稀土氧化物 Y2O3 改性 g-C3N4 用于高效光催化制氢：光催化性能和电子传递通道

Semiconductor Science and Technology Pub Date : 2024-07-15 DOI: 10.1088/1361-6641/ad634b

F. Niu, Ziyang Zhang, W. Lei, Jiashuang Li, Baoxiang Wang, Yi Shen

引用次数: 0

Atmospheric Neutron-induced Single Event Burnout Characterization of 4.5 kV Si IGBTs with Spallation Neutron Irradiation 利用溅射中子辐照对 4.5 kV Si IGBT 进行大气中子诱发的单次烧毁表征

Semiconductor Science and Technology Pub Date : 2024-07-15 DOI: 10.1088/1361-6641/ad634c

Chao Peng, Liu Yang, Zhifeng Lei, Yuebin Zhou, Teng Ma, Zhiyong Yuan, Zhangang Zhang, Yujuan He, Yun Huang

引用次数: 0

Research of single-event burnout in vertical Ga2O3 FinFET by low carrier lifetime control 通过低载流子寿命控制研究垂直 Ga2O3 FinFET 中的单次烧毁现象

Semiconductor Science and Technology Pub Date : 2024-07-10 DOI: 10.1088/1361-6641/ad617c

Yun Can Bao, Cheng-hao Yu, Wen-sheng Zhao, Xiao Dong Wu, Xin Tan, Hui Yang

{"title":"Research of single-event burnout in vertical Ga2O3 FinFET by low carrier lifetime control","authors":"Yun Can Bao, Cheng-hao Yu, Wen-sheng Zhao, Xiao Dong Wu, Xin Tan, Hui Yang","doi":"10.1088/1361-6641/ad617c","DOIUrl":"https://doi.org/10.1088/1361-6641/ad617c","url":null,"abstract":"\u0000 This paper presents the 2-D simulations of single-event burnout (SEB) in vertical enhancement-mode gallium oxide (Ga2O3) fin-shaped channels field-effect transistor (FinFET) by low carrier lifetime control (LCLC) method. The correctness of the structure parameters and simulated physical models are verified by the basic electrical characteristics in experiments. The SEB simulations show that the most sensitive region to heavy ion is the narrow channel region. The SEB failure is due to the diffusion of a large number of electron-hole pairs induced by heavy ion into a strong electric field region, resulting in a large transient current density to cause the thermal failure. Afterwards, the influences of the narrow channel region width on basic characteristics and SEB performance are discussed. Then, the SEB hardening mechanism of LCLC is studied that the electric field peak in the top of the structure can be effectively reduced, and the transient current caused by second avalanche is restrained. In addition, the basic characteristics with LCLC are proved to be hardly influenced in Ga2O3 FinFET. Finally, the carrier lifetime value and local control region are studied that the SEB hardening performance can be significantly improved by a large enough control area with a low carrier lifetime.","PeriodicalId":507064,"journal":{"name":"Semiconductor Science and Technology","volume":"19 2","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141660926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel MTCMOS based 8T2M NVSRAM design for low power applications with high temperature endurance 基于 MTCMOS 的新型 8T2M NVSRAM 设计，适用于具有高温耐久性的低功耗应用

Semiconductor Science and Technology Pub Date : 2024-07-09 DOI: 10.1088/1361-6641/ad60f0

Udayan Chakraborty, Tanmoy Majumder, Rupanjal Debbarma, N. Das, Abhishek Bhattacharjee

引用次数: 0

Failure mechanisms of the thyristor switch in pulsed arc electrohydraulic discharges 脉冲电弧电液放电中晶闸管开关的失效机制

Semiconductor Science and Technology Pub Date : 2024-07-05 DOI: 10.1088/1361-6641/ad5fb0

Yingbo Yu, Zhongjian Kang

{"title":"Failure mechanisms of the thyristor switch in pulsed arc electrohydraulic discharges","authors":"Yingbo Yu, Zhongjian Kang","doi":"10.1088/1361-6641/ad5fb0","DOIUrl":"https://doi.org/10.1088/1361-6641/ad5fb0","url":null,"abstract":"\u0000 In order to study the failure mechanism of the thyristor switch in the application of electric pulse fracturing, an underwater pulse power discharge experimental platform was built, the impedance characteristics of the plasma channel were analyzed and the circuit equivalence was carried out for each discharge stage. Then, based on the Silvaco simulation software, a theoretical thyristor model was established. By observing the distribution of the internal carriers and current density, the turnon and turn-off processes of the thyristor switch under high voltage were analyzed. The formation factors of peak voltage in the turn-off process were studied, the easy breakdown position was pointed out, and a method to suppress the reverse peak voltage by creating critical damping oscillations in the discharge circuit was proposed. Finally, a pulsed power discharge experiment was carried out to verify the theoretical analysis. The experimental results show that the discharge waveform conforms to the theoretical analysis, and the high voltage breakdown damage of the thyristor is also consistent with the theoretical simulation model. Furthermore, the proposed thyristor protection method can greatly suppress the reverse voltage spike, reduce the peak voltage by 52%, and effectively avoid the damage caused by withstand voltage breakdown in the application of pulse power discharge.","PeriodicalId":507064,"journal":{"name":"Semiconductor Science and Technology","volume":" 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141673444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Demonstration of a lateral p-NiO/n-GaN JFET fabricated by selective-area regrowth 展示通过选择性区域再生长技术制造的横向 p-NiO/n-GaN JFET

Semiconductor Science and Technology Pub Date : 2024-07-04 DOI: 10.1088/1361-6641/ad5f52

Guang Qiao, Jing Yu, Lin Hao, Ailin Miao, Liang Xu, Hong Zhu, Zili Xie

引用次数: 0

Exploration and optimization of novel replacement and prefetching strategies for inefficiencies of advanced MRAM-based hybrid cache systems 探索和优化新型替换和预取策略，解决基于 MRAM 的先进混合高速缓存系统效率低下的问题

Semiconductor Science and Technology Pub Date : 2024-05-24 DOI: 10.1088/1361-6641/ad5043

Shaopu Han, Yanfeng Jiang

{"title":"Exploration and optimization of novel replacement and prefetching strategies for inefficiencies of advanced MRAM-based hybrid cache systems","authors":"Shaopu Han, Yanfeng Jiang","doi":"10.1088/1361-6641/ad5043","DOIUrl":"https://doi.org/10.1088/1361-6641/ad5043","url":null,"abstract":"\u0000 With the emergence of cutting-edge hardware systems such as cloud computing, edge computing, and on-chip neural network accelerators, how to design advanced memory strategies to substitute the traditional ones for maximizing the potential performance of non-volatile memory (NVM) under the existing hardware conditions, has become an urgent research issue for both academia and industrial communities. It is promising and innovative to improve computer systems in the layer of data exchanging with the emerging advanced semiconductor devices. In the paper, to address the inefficiencies of write-intensive, high power consumption, low hit rate and so on, which exist in hybrid Magnetic Random Access Memory (MRAM) cache systems, three novel cache replacement strategies and two cache prefetching strategies are put forward. The proposed triple novel replacement strategies, including historical frequency and time judgments, duplicate data-aware deletion, and dynamic relevance factors computing, can be utilized to compensate for the shortcomings of the traditional Least Recently Used (LRU) replacement strategy, respectively. In the two novel prefetching strategies, region distribution parameters and Listnet ranking network are imported into the caching process, respectively, to achieve optimized hitting performance. The simulation results demonstrate that the proposed replacement strategies can achieve up to 61.76%, 84.91%, 56.49%, and 53.21% optimization of write count, hit rate, dynamic power, and IPC compared to the conventional one. The proposed prefetching strategy can achieve up to 91.27%, 49.25% hit rate and IPC optimization. Meanwhile, the synthetic evaluation of the replacement and prefetching strategies are elaborated in the paper, including multi-core characteristics, information entropy, interplays and the performance constraints between replacement and prefetching mechanism, which would facilitate more credible ideas for future memory inefficiencies management and strategy design.","PeriodicalId":507064,"journal":{"name":"Semiconductor Science and Technology","volume":"12 3","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141098774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Performance enhancement of nanotube junctionless FETs with low doping concentration rings 利用低掺杂浓度环提高纳米管无结场效应晶体管的性能

Semiconductor Science and Technology Pub Date : 2024-05-24 DOI: 10.1088/1361-6641/ad5042

Liang Wang, Wanyang Xiao, Yueyang Wang, YongLin Bai, Zirui Wang, Jie Xu, Min Tang, Qiuxiang Zhang, Weijing Liu, Wei Bai, Xiaodong Tang

{"title":"Performance enhancement of nanotube junctionless FETs with low doping concentration rings","authors":"Liang Wang, Wanyang Xiao, Yueyang Wang, YongLin Bai, Zirui Wang, Jie Xu, Min Tang, Qiuxiang Zhang, Weijing Liu, Wei Bai, Xiaodong Tang","doi":"10.1088/1361-6641/ad5042","DOIUrl":"https://doi.org/10.1088/1361-6641/ad5042","url":null,"abstract":"\u0000 To reduce the static power consumption of the NT JLFET and the effect of SCEs on the NT JLFET, A nanotube junctionless field effect transistor with cyclic low doping concentration regions (C NT JLFET) is proposed. Based on Sentaurus TCAD numerical simulations, the electrical properties of the C NT JLFET and the NT JLFET were comparatively investigated, and the effects of the length (LCD) and radius (RCD) of cyclic low doping concentration regions on the electrical properties of the C NT JLFETs were studied. The C NT JLFET reduces the gate-induced drain leakage (GIDL) due to lateral band-to-band-tunneling (L-BTBT) as compared to the NT JLFET. As the LCD or RCD increases, the off-state current decreases. In addition, the C NT JLFET suffers from fewer short channel effects (SCEs), such as threshold voltage roll-off, drain-induced barrier lowering and subthreshold swing deterioration, compared to the NT JLFET. The inhibition of L-BTBT and attenuation of SCEs by cyclic low doping concentration regions remains when the channel length of the C NT JLFET is shortened to 10 nm. The C NT JLFET are suitable for low power applications as they exhibit reduced L-BTBT and suffer from fewer SCEs.","PeriodicalId":507064,"journal":{"name":"Semiconductor Science and Technology","volume":"8 7","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141100144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0