探索和优化新型替换和预取策略,解决基于 MRAM 的先进混合高速缓存系统效率低下的问题

Shaopu Han, Yanfeng Jiang
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摘要

随着云计算、边缘计算和片上神经网络加速器等尖端硬件系统的出现,如何设计先进的内存策略来替代传统内存策略,从而在现有硬件条件下最大限度地发挥非易失性内存(NVM)的潜在性能,已成为学术界和工业界亟待解决的研究课题。利用新兴的先进半导体器件改进计算机系统的数据交换层,是一项前景广阔的创新工作。本文针对混合磁随机存取存储器(MRAM)高速缓存系统存在的写入密集、功耗高、命中率低等低效问题,提出了三种新型高速缓存替换策略和两种高速缓存预取策略。所提出的三种新型替换策略,包括历史频率和时间判断、重复数据感知删除和动态相关因素计算,可分别用于弥补传统的最近最少使用(LRU)替换策略的不足。在这两种新型预取策略中,分别将区域分布参数和列表网排名网络引入缓存过程,以实现优化的命中性能。仿真结果表明,与传统策略相比,所提出的替换策略在写入次数、命中率、动态功耗和 IPC 方面分别实现了高达 61.76%、84.91%、56.49% 和 53.21% 的优化。所提出的预取策略可实现高达 91.27% 的命中率和 49.25% 的 IPC 优化。同时,文中还对替换和预取策略进行了合成评估,包括多核特性、信息熵、相互影响以及替换和预取机制之间的性能约束等,这将为未来的内存低效管理和策略设计提供更可靠的思路。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Exploration and optimization of novel replacement and prefetching strategies for inefficiencies of advanced MRAM-based hybrid cache systems
With the emergence of cutting-edge hardware systems such as cloud computing, edge computing, and on-chip neural network accelerators, how to design advanced memory strategies to substitute the traditional ones for maximizing the potential performance of non-volatile memory (NVM) under the existing hardware conditions, has become an urgent research issue for both academia and industrial communities. It is promising and innovative to improve computer systems in the layer of data exchanging with the emerging advanced semiconductor devices. In the paper, to address the inefficiencies of write-intensive, high power consumption, low hit rate and so on, which exist in hybrid Magnetic Random Access Memory (MRAM) cache systems, three novel cache replacement strategies and two cache prefetching strategies are put forward. The proposed triple novel replacement strategies, including historical frequency and time judgments, duplicate data-aware deletion, and dynamic relevance factors computing, can be utilized to compensate for the shortcomings of the traditional Least Recently Used (LRU) replacement strategy, respectively. In the two novel prefetching strategies, region distribution parameters and Listnet ranking network are imported into the caching process, respectively, to achieve optimized hitting performance. The simulation results demonstrate that the proposed replacement strategies can achieve up to 61.76%, 84.91%, 56.49%, and 53.21% optimization of write count, hit rate, dynamic power, and IPC compared to the conventional one. The proposed prefetching strategy can achieve up to 91.27%, 49.25% hit rate and IPC optimization. Meanwhile, the synthetic evaluation of the replacement and prefetching strategies are elaborated in the paper, including multi-core characteristics, information entropy, interplays and the performance constraints between replacement and prefetching mechanism, which would facilitate more credible ideas for future memory inefficiencies management and strategy design.
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