IET Computers and Digital Techniques最新文献

{"title":"Residual vulnerabilities to power side channel attacks of lightweight ciphers cryptography competition finalists","authors":"Aurelien T. Mozipo,&nbsp;John M. Acken","doi":"10.1049/cdt2.12057","DOIUrl":"https://doi.org/10.1049/cdt2.12057","url":null,"abstract":"<p>The protection of communications between Internet of Things (IoT) devices is of great concern because the information exchanged contains vital sensitive data. Malicious agents seek to exploit those data to extract secret information about the owners or the system. Power side channel attacks are of great concern on these devices because their power consumption unintentionally leaks information correlatable to the device's secret data. Several studies have demonstrated the effectiveness of authenticated encryption with advanced data, in protecting communications with these devices. A comprehensive evaluation of the seven (out of 10) algorithm finalists of the National Institute of Standards and Technology (NIST) IoT lightweight cipher competition that do not integrate built-in countermeasures is proposed. The study shows that, nonetheless, they still present some residual vulnerabilities to power side channel attacks (SCA). For five ciphers, an attack methodology as well as the leakage function needed to perform correlation power analysis (CPA) is proposed. The authors assert that Ascon, Sparkle, and PHOTON-Beetle security vulnerability can generally be assessed with the security assumptions “Chosen ciphertext attack and leakage in encryption only, with nonce-misuse resilience adversary (CCAmL1)” and “Chosen ciphertext attack and leakage in encryption only with nonce-respecting adversary (CCAL1)”, respectively. However, the security vulnerability of GIFT-COFB, Grain, Romulus, and TinyJambu can be evaluated more straightforwardly with publicly available leakage models and solvers. They can also be assessed simply by increasing the number of traces collected to launch the attack.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"17 3-4","pages":"75-88"},"PeriodicalIF":1.2,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12057","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50141094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient implementation of low cost and secure framework with firmware updates","authors":"Ines Ben Hlima,&nbsp;Halim Kacem,&nbsp;Ali Gharsallah","doi":"10.1049/cdt2.12054","DOIUrl":"https://doi.org/10.1049/cdt2.12054","url":null,"abstract":"<p>Recently, the Internet of things (IoT) has become extensively used in our daily lives. This technology offers a new vision of the future internet where devices are interconnected and can communicate together. A big number of these devices complicates the firmware update and makes it more expensive since each node must be updated locally. Nevertheless, there are many cases where devices cannot change their location to upgrade the firmware locally due to an unreachable location or dangerous place. Therefore, it is necessary to remotely update the firmware of devices. In this study, the authors propose an efficient implementation of a low cost and secure framework of upgrading the firmware employing the latter On-The-Air programming technique. The authors present a proof of concept for a ubiquitous system applying wireless programmer. Our design offers a remote broadcasting of image code without disturbing the main functionality of nodes. The authors validated the performance of our design on a real network based on STM32 micro-controllers. The results showed the reduction of the network time-off, enabling a continuous operation of the ecosystem.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"17 3-4","pages":"89-99"},"PeriodicalIF":1.2,"publicationDate":"2023-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12054","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50147647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ActiveGuard: An active intellectual property protection technique for deep neural networks by leveraging adversarial examples as users' fingerprints","authors":"Mingfu Xue,&nbsp;Shichang Sun,&nbsp;Can He,&nbsp;Dujuan Gu,&nbsp;Yushu Zhang,&nbsp;Jian Wang,&nbsp;Weiqiang Liu","doi":"10.1049/cdt2.12056","DOIUrl":"https://doi.org/10.1049/cdt2.12056","url":null,"abstract":"<p>The intellectual properties (IP) protection of deep neural networks (DNN) models has raised many concerns in recent years. To date, most of the existing works use DNN watermarking to protect the IP of DNN models. However, the DNN watermarking methods can only passively verify the copyright of the model after the DNN model has been pirated, which cannot prevent piracy in the first place. In this paper, an active DNN IP protection technique against DNN piracy, called ActiveGuard<i>,</i> is proposed. ActiveGuard can provide active authorisation control, users' identities management, and ownership verification for DNN models. Specifically, for the first time, ActiveGuard exploits well-crafted rare and specific adversarial examples with specific classes and confidences as users' fingerprints to distinguish authorised users from unauthorised ones. Authorised users can input their fingerprints to the DNN model for identity authentication and then obtain normal usage, while unauthorised users will obtain a very poor model performance. In addition, ActiveGuard enables the model owner to embed a watermark into the weights of the DNN model for ownership verification. Compared to the few existing active DNN IP protection works, ActiveGuard can support both users' identities identification and active authorisation control. Besides, ActiveGuard introduces lower overhead than these existing active protection works. Experimental results show that, for authorised users, the test accuracy of LeNet-5 and Wide Residual Network (WRN) models are 99.15% and 91.46%, respectively, while for unauthorised users, the test accuracy of LeNet-5 and WRN models are only 8.92% and 10%, respectively. Besides, each authorised user can pass the fingerprint authentication with a high success rate (up to 100%). For ownership verification, the embedded watermark can be successfully extracted, while the normal performance of DNN models will not be affected. Furthermore, it is demonstrated that ActiveGuard is robust against model fine-tuning attack, pruning attack, and three types of fingerprint forgery attacks.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"17 3-4","pages":"111-126"},"PeriodicalIF":1.2,"publicationDate":"2023-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12056","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50147648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fast approximation of the top-k items in data streams using FPGAs","authors":"Ali Ebrahim,&nbsp;Jalal Khalifat","doi":"10.1049/cdt2.12053","DOIUrl":"https://doi.org/10.1049/cdt2.12053","url":null,"abstract":"<p>Two methods are presented for finding the top-<i>k</i> items in data streams using Field Programmable Gate Arrays (FPGAs). These methods deploy two variants of a novel accelerator architecture capable of extracting an approximate list of the topmost frequently occurring items in a single pass over the input stream without the need for random access. The first variant of the accelerator implements the well-known <i>Probabilistic</i> sampling algorithm by mapping its main processing stages to a hardware architecture consisting of two custom systolic arrays. The proposed architecture retains all the properties of this algorithm, which works even if the stream size is unknown at run time. The architecture shows better scalability compared to other architectures that are based on other stream algorithms. In addition, experimental results on both synthetic and real datasets, when implementing the accelerator on an Intel Arria 10 GX 1150 FPGA device, showed very good accuracy and significant throughput gains compared to the existing software and hardware-accelerated solutions. The second variant of the accelerator is specifically tailored for applications requiring higher accuracy, provided that the size of the stream is known at run time. This variant takes advantage of the embedded memory resources in an FPGA to implement a sketch-based filter that precedes the main systolic array in the accelerator's pipeline. This filter enhances the accuracy of the accelerator by pre-processing the stream to remove much of the insignificant items, allowing the accelerator to process a significantly smaller filtered stream.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"17 2","pages":"60-73"},"PeriodicalIF":1.2,"publicationDate":"2023-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12053","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50152328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Phone-nomenon 2.0: A compact thermal model for smartphones","authors":"Yu-Min Lee,&nbsp;Hong-Wen Chiou,&nbsp;Shinyu Shiau,&nbsp;Chi-Wen Pan,&nbsp;Shih-Hung Ting","doi":"10.1049/cdt2.12052","DOIUrl":"https://doi.org/10.1049/cdt2.12052","url":null,"abstract":"<p>This paper presents a compact thermal model for smartphones, Phone-nomenon 2.0, to predict the thermal behavior of smartphones. In the beginning, non-linearities of internal and external heat transfer mechanisms of smartphones and a compact thermal model for these non-linearities have been studied and proposed. Then, an iterative simulation procedure to handle these non-linearities was developed, and the basic simulation framework which is one option in Phone-nomenon 2.0 was established and we call it Phone-nomenon.Iter. Finally, the linearisation approach was applied, and model order reduction techniques to enhance and speed up the basic framework were employed, and these two options Phone-nomenon.Lin and Phone-nomenon.LinMOR were named. Compared with a commercial tool, ANSYS Icepak, Phone-nomenon.Iter can achieve two orders of magnitude speedup with the maximum error being less than 1.90% for steady-state simulations and three orders of magnitude speedup with the temperature difference being less than 0.65°C for transient simulations. In addition, the speedup of Phone-nomenon.Lin over Phone-nomenon.Iter can be at least 4.22× and 3.26× for steady-state and transient simulations, respectively. Moreover, the speedup of Phone-nomenon.LinMOR over Phone-nomenon.Lin is at least 2.57×.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"17 2","pages":"43-59"},"PeriodicalIF":1.2,"publicationDate":"2023-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12052","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50125052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Machine learning guided thermal management of Open Computing Language applications on CPU-GPU based embedded platforms","authors":"Rakesh Kumar,&nbsp;Bibhas Ghoshal","doi":"10.1049/cdt2.12050","DOIUrl":"https://doi.org/10.1049/cdt2.12050","url":null,"abstract":"<p>As embedded devices start supporting heterogeneous processing cores (Central Processing Unit [CPU]–Graphical Processing Unit [GPU] based cores), performance aware task allocation becomes a major issue. Use of Open Computing Language (OpenCL) applications on both CPU and GPU cores improves performance and resolves the problem. However, it has an adverse effect on the overall power consumption and the operating temperature of the system. Operating both kind of cores within a small form factor at high frequency causes rise in power consumption which in turn leads to increase in processor temperature. The elevated temperature brings about major thermal issues. In this paper, we present our investigation on the role of CPU during execution of GPU specific application and argue against running it at the high frequency. In addition, a machine learning guided mechanism to predict the optimal operating frequency of CPU cores during execution of OpenCL GPU kernels is presented in this study. Our experiments with OpenCL applications on the state of the art <i>ODROID XU4</i> embedded platform show that the CPU cores of the experimental board if operated at a frequency proposed by our Machine Learning-based predictive method brings about 12.5°C reduction in processor temperature at 1.06% degradation in performance compared to the baseline frequency (default <i>performance</i> frequency governor of the embedded platform).</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"17 1","pages":"20-28"},"PeriodicalIF":1.2,"publicationDate":"2022-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12050","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50155184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Event-based high throughput computing: A series of case studies on a massively parallel softcore machine","authors":"Mark Vousden,&nbsp;Jordan Morris,&nbsp;Graeme McLachlan Bragg,&nbsp;Jonathan Beaumont,&nbsp;Ashur Rafiev,&nbsp;Wayne Luk,&nbsp;David Thomas,&nbsp;Andrew Brown","doi":"10.1049/cdt2.12051","DOIUrl":"https://doi.org/10.1049/cdt2.12051","url":null,"abstract":"<p>This paper introduces an event-based computing paradigm, where workers only perform computation in response to external stimuli (events). This approach is best employed on hardware with many thousands of smaller compute cores with a fast, low-latency interconnect, as opposed to traditional computers with fewer and faster cores. Event-based computing is timely because it provides an alternative to traditional big computing, which suffers from immense infrastructural and power costs. This paper presents four case study applications, where an event-based computing approach finds solutions to orders of magnitude more quickly than the equivalent traditional big compute approach, including problems in computational chemistry and condensed matter physics.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"17 1","pages":"29-42"},"PeriodicalIF":1.2,"publicationDate":"2022-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12051","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50137733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Voltage over-scaling CNT-based 8-bit multiplier by high-efficient GDI-based counters","authors":"Ayoub Sadeghi,&nbsp;Nabiollah Shiri,&nbsp;Mahmood Rafiee,&nbsp;Abdolreza Darabi,&nbsp;Ebrahim Abiri","doi":"10.1049/cdt2.12049","DOIUrl":"https://doi.org/10.1049/cdt2.12049","url":null,"abstract":"<p>A new low-power and high-speed multiplier is presented based on the voltage over scaling (VOS) technique and new 5:3 and 7:3 counter cells. The VOS reduces power consumption in digital circuits, but different voltage levels of the VOS increase the delay in different stages of a multiplier. Hence, the proposed counters are implemented by the gate-diffusion input technique to solve the speed limitation of the VOS-based circuits. The proposed GDI-based 5:3 and 7:3 counters save power and reduce the area by 2x and 2.5x, respectively. To prevent the threshold voltage (<i>V</i>_th) drop in the suggested GDI-based circuits, carbon nanotube field-effect transistor (CNTFET) technology is used. In the counters, the chirality vector and tubes of the CNTFETs are properly adjusted to attain full-swing outputs with high driving capability. Also, their validation against heat distribution under different time intervals, as a major issue in the CNTFET technology is investigated, and their very low sensitivity is confirmed. The low complexity, high stability and efficient performance of the presented counter cells introduce the proposed VOS-CNTFET-GDI-based multiplier as an alternative to the previous designs.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"17 1","pages":"1-19"},"PeriodicalIF":1.2,"publicationDate":"2022-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12049","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50146867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A four-stage yield optimization technique for analog integrated circuits using optimal computing budget allocation and evolutionary algorithms","authors":"Abbas Yaseri,&nbsp;Mohammad Hossein Maghami,&nbsp;Mehdi Radmehr","doi":"10.1049/cdt2.12048","DOIUrl":"10.1049/cdt2.12048","url":null,"abstract":"<p>A high yield estimation is necessary for designing analogue integrated circuits. In the Monte-Carlo (MC) method, many transistor-level simulations should be performed to obtain the desired result. Therefore, some methods are needed to be combined with MC simulations to reach high yield with high speed at the same time. In this paper, a four-stage yield optimisation approach is presented, which employs computational intelligence to accelerate yield estimation without losing accuracy. Firstly, the designs that met the desired characteristics are provided using critical analysis (CA). The aim of utilising CA is to avoid unnecessary MC simulations repeating for non-critical solutions. Then in the second and third stages, the shuffled frog-leaping algorithm and the Non-dominated Sorting Genetic Algorithm-III are proposed to improve the performance. Finally, MC simulations are performed to present the final result. The yield value obtained from the simulation results for two-stage class-AB Operational Transconductance Amplifer (OTA) in 180 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology is 99.85%. The proposed method has less computational effort and high accuracy than the MC-based approaches. Another advantage of using CA is that the initial population of multi-objective optimisation algorithms will no longer be random. Simulation results prove the efficiency of the proposed technique.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"16 5-6","pages":"183-195"},"PeriodicalIF":1.2,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12048","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87528214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Illegal Trojan design and detection in asynchronous NULL Convention Logic and Sleep Convention Logic circuits","authors":"Kushal K. Ponugoti,&nbsp;Sudarshan K. Srinivasan,&nbsp;Scott C. Smith,&nbsp;Nimish Mathure","doi":"10.1049/cdt2.12047","DOIUrl":"10.1049/cdt2.12047","url":null,"abstract":"<p>With Cyber warfare, detection of hardware Trojans, malicious digital circuit components that can leak data and degrade performance, is an urgent issue. Quasi-Delay Insensitive asynchronous digital circuits, such as NULL Convention Logic (NCL) and Sleep Convention Logic, also known as Multi-Threshold NULL Convention Logic (MTNCL), have inherent security properties and resilience to large fluctuations in temperatures, which make them very alluring to extreme environment applications, such as space exploration, automotive, power industry etc. This paper shows how dual-rail encoding used in NCL and MTNCL can be exploited to design Trojans, which would not be detected using existing methods. Generic threat models for Trojans are given. Formal verification methods that are capable of accurate detection of Trojans at the Register-Transfer-Level are also provided. The detection methods were tested by embedding Trojans in NCL and MTNCL Rivest-Shamir-Adleman (RSA) decryption circuits. The methods were applied to 25 NCL and 25 MTNCL RSA benchmarks of various data path width and provided 100% rate of detection.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"16 5-6","pages":"172-182"},"PeriodicalIF":1.2,"publicationDate":"2022-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12047","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85767635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}