Residual vulnerabilities to power side channel attacks of lightweight ciphers cryptography competition finalists

IF 1.1 4区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Aurelien T. Mozipo, John M. Acken
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引用次数: 1

Abstract

The protection of communications between Internet of Things (IoT) devices is of great concern because the information exchanged contains vital sensitive data. Malicious agents seek to exploit those data to extract secret information about the owners or the system. Power side channel attacks are of great concern on these devices because their power consumption unintentionally leaks information correlatable to the device's secret data. Several studies have demonstrated the effectiveness of authenticated encryption with advanced data, in protecting communications with these devices. A comprehensive evaluation of the seven (out of 10) algorithm finalists of the National Institute of Standards and Technology (NIST) IoT lightweight cipher competition that do not integrate built-in countermeasures is proposed. The study shows that, nonetheless, they still present some residual vulnerabilities to power side channel attacks (SCA). For five ciphers, an attack methodology as well as the leakage function needed to perform correlation power analysis (CPA) is proposed. The authors assert that Ascon, Sparkle, and PHOTON-Beetle security vulnerability can generally be assessed with the security assumptions “Chosen ciphertext attack and leakage in encryption only, with nonce-misuse resilience adversary (CCAmL1)” and “Chosen ciphertext attack and leakage in encryption only with nonce-respecting adversary (CCAL1)”, respectively. However, the security vulnerability of GIFT-COFB, Grain, Romulus, and TinyJambu can be evaluated more straightforwardly with publicly available leakage models and solvers. They can also be assessed simply by increasing the number of traces collected to launch the attack.

Abstract Image

轻量级密码密码学竞赛决赛选手的电源侧信道攻击残余漏洞
物联网(IoT)设备之间的通信保护备受关注,因为交换的信息包含重要的敏感数据。恶意代理试图利用这些数据来提取有关所有者或系统的秘密信息。功率侧信道攻击在这些设备上引起了极大的关注,因为它们的功耗无意中泄露了与设备的秘密数据相关的信息。几项研究已经证明了使用高级数据进行身份验证加密在保护与这些设备的通信方面的有效性。对美国国家标准与技术研究院(NIST)物联网轻量级密码竞赛的七名(满分10名)算法决赛选手进行了综合评估,这些选手没有集成内置对策。研究表明,尽管如此,它们仍然存在一些对功率侧信道攻击(SCA)的残余漏洞。针对五种密码,提出了一种攻击方法以及执行相关功率分析(CPA)所需的泄漏函数。作者断言,Ascon、Sparkle和PHOTON Beetle的安全漏洞通常可以分别根据安全假设“仅在加密中选择密文攻击和泄漏,具有随机数滥用弹性对手(CCAmL1)”和“仅在尊重随机数的对手(CCAL1)的加密中选择密码攻击和泄漏”进行评估。然而,GIFT-COFB、Grain、Romulus和TinyJambu的安全漏洞可以使用公开的泄漏模型和求解器进行更直接的评估。也可以简单地通过增加为发动攻击而收集的痕迹数量来评估它们。
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来源期刊
IET Computers and Digital Techniques
IET Computers and Digital Techniques 工程技术-计算机:理论方法
CiteScore
3.50
自引率
0.00%
发文量
12
审稿时长
>12 weeks
期刊介绍: IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test. The key subject areas of interest are: Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues. Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware. Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting. Case Studies: emerging applications, applications in industrial designs, and design frameworks.
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