IET Computers and Digital Techniques最新文献

{"title":"Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGP","authors":"H. C. Prashanth,&nbsp;Madhav Rao","doi":"10.1049/2024/6623637","DOIUrl":"10.1049/2024/6623637","url":null,"abstract":"<div>\u0000 <p>Unconventional functions, including activation functions and power functions, are extremely hard-to-realize primarily due to the difficulty in arriving at the hierarchical design. The hierarchical design allows the synthesis tool to map the functionality with that of standard cells employed through the regular ASIC synthesis flow. For conventional functions, the hierarchical design is structured and then supplied to the synthesis flow, whereas, for unconventional functions, the same method is not reliable, since the current synthesis method does not offer any design-space exploration scheme to arrive at an easy-to-realize design entity. The unconventional functions either take a long synthesis run-time or additional efforts are spent in restructuring the hierarchical design for the desired function to synthesizable ones. Cartesian genetic programing (CGP) allows to not only incorporate custom logic gates for synthesizing the hierarchical design but also aids in the design-space exploration for the targeted function through the custom gates. The CGP configuration evolves difficult-to-realize complex functions with multiple solutions, and filtering through desired Pareto-optimal requirements offers a unique hierarchical design. Incorporating CGP-derived hierarchical designs into the traditional synthesis flow is instrumental for implementing and evaluating higher-order designs comprising nonlinear functional constructs. Six activation functions and power functions that fall in the category of unconventional functions are realized by the CGP method using custom cells to demonstrate the capability. Further, the hierarchical design of these unconventional functions is flattened and compared with the same function that is directly synthesized using basic gates. The CGP-derived synthesis method reports 3× less synthesis time for realizing the complex functions at the hierarchical level compared to the synthesis using basic gate cells. Hardware characteristics and error metrics are also investigated for the CGP realized complex functions and are made freely available for further usage to the research and designers’ community.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"2024 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2024-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/2024/6623637","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140486715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Fast Fully Parallel Ant Colony Optimization Algorithm Based on CUDA for Solving TSP","authors":"Zhi Zeng,&nbsp;Yuxing Cai,&nbsp;Kwok L. Chung,&nbsp;Hui Lin,&nbsp;Jinwei Wu","doi":"10.1049/2023/9915769","DOIUrl":"https://doi.org/10.1049/2023/9915769","url":null,"abstract":"<div>\u0000 <p>In view of the known problems of parameter sensitivity, local optimum, and slow convergence in the ant colony optimization (ACO), we aim to improve the performance of the ACO. To solve the traveling salesman problem (TSP) quickly with accurate results, we propose a fully parallel ACO (FP-ACO). Based on the max–min ant system (MMAS), we initiate a compensation mechanism for pheromone to constrain its value, guarantee the correctness of results and avoid a local optimum, and further enhance the convergence ability of ACO. Moreover, based on the compute unified device architecture (CUDA), the ACO is implemented as a kernel function on a graphics processing unit (GPU), which shortens the running time of massive iterations. Combined with the roulette wheel selection mechanism, FP-ACO has powerful search capabilities and is committed to obtaining better solutions. The experimental results show that, compared with the effective strategies ACO (ESACO) that runs on CPU, the speed-up ratio of the proposed algorithm reaches 35, and the running time is less than that of the max–min ant system-roulette wheel method-bitmask tabu (MMAS-RWM-BT) that runs on GPU. Furthermore, our algorithm outperforms the other two algorithms in the speed-up ratio and less runtime, proving that the proposed FP-ACO is more suitable for solving TSP.</p>\u0000 </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"2023 1","pages":""},"PeriodicalIF":1.1,"publicationDate":"2023-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/2023/9915769","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143253893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multi-objective digital circuit block optimisation based on cell mapping in an industrial electronic design automation flow","authors":"Linan Cao,&nbsp;Simon J. Bale,&nbsp;Martin A. Trefzer","doi":"10.1049/cdt2.12062","DOIUrl":"https://doi.org/10.1049/cdt2.12062","url":null,"abstract":"<p>Modern electronic design automation (EDA) tools can handle the complexity of state-of-the-art electronic systems by decomposing them into smaller blocks or cells, introducing different levels of abstraction and staged design flows. However, throughout each independently optimised design step, overheads and inefficiencies can accumulate in the resulting overall design. Performing design-specific optimisation from a more global viewpoint requires more time due to the larger search space but has the potential to provide solutions with improved performanc. In this work, a fully-automated, multi-objective (MO) EDA flow is introduced to address this issue. It specifically tunes drive strength mapping, prior to physical implementation, through MO population-based search algorithms. Designs are evaluated with respect to their power, performance and area (PPA). The proposed approach is aimed at digital circuit optimisation at the block level, where it is capable of expanding the design space and offers a set of trade-off solutions for different case-specific utilisation. We have applied the proposed multi-objective electronic design automation flow (MOEDA) framework to ISCAS-85 and EPFL benchmark circuits by using a commercial 65 nm standard cell library. The experimental results demonstrate how the MOEDA flow enhances the solutions initially generated by the standard digital flow and how simultaneously a significant improvement in PPA metrics is achieved.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"17 3-4","pages":"180-194"},"PeriodicalIF":1.2,"publicationDate":"2023-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12062","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50144641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and analysis of a novel fast adder using logical effort method","authors":"Hamid Tavakolaee,&nbsp;Gholamreza Ardeshir,&nbsp;Yasser Baleghi","doi":"10.1049/cdt2.12063","DOIUrl":"https://doi.org/10.1049/cdt2.12063","url":null,"abstract":"<p>Addition, as one of the fundamental math operations, is applied widely in Very-large-scale integration systems and digital signal processing, such that the computational speed of a system depends mainly on the computational speed of its adders. There are various types of digital adders based on different methods. A novel adder is proposed which performs addition based on a path with a fewer number of levels, and, hence, with higher computational speed and lower power consumption. The goal and innovation is to design a structured fast adder that has a block that can be expanded to higher bits, and in this design, the calculation speed and power consumption of the proposed circuit are optimal. Each proposed adder circuit has several levels, and the formulae of each level are stated. Each level of the circuit is designed with a number of multiplexers and OR gates. The performance of the proposed adder has been investigated and evaluated in two parts of mathematical calculations and simulation, and it has also been compared with other existing fast adders, such as ripple carry adder, carry skip adder, carry select adder, carry look ahead adder and prefix kogge-stone in cases of 8, 16, 32 and 64 bits. The results show that the proposed collector has a good performance compared to other adders-based power consumption, power delay product and delay area product metrics.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"17 3-4","pages":"195-208"},"PeriodicalIF":1.2,"publicationDate":"2023-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12063","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50137809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reconstructing a lightweight security protocol in the radio-frequency identification systems","authors":"Alireza Abdellahi Khorasgani,&nbsp;Mahdi Sajadieh,&nbsp;Mohammad Rouhollah Yazdani","doi":"10.1049/cdt2.12064","DOIUrl":"https://doi.org/10.1049/cdt2.12064","url":null,"abstract":"<p>Nowadays, the Internet of things (IoT) has extensively found its way into everyday life, raising the alarm regarding data security and user privacy. However, IoT devices have numerous limitations that inhibit the implementation of optimal cost-effective security solutions. In recent years, researchers have proposed a small number of RFID-based (radio-frequency identification) security solutions for the IoT. The use of RFID to secure IoT systems is growing rapidly, for it provides small-scale efficient security mechanisms. Due to the importance of privacy and security in IoT systems, Chuang and Tu have proposed a lightweight authentication protocol using XCor operation. The purpose is to investigate the security of the mentioned protocol and to show the problems of XCor operations used in this protocol. The authors reveal its vulnerability to various attacks, such as tag impersonation, reader impersonation and de−synchronisation attacks. To solve the problems of the Chuang protocol, a secure authentication protocol that uses the lightweight Plr operation is proposed. A formal security analysis of this protocol is performed based on the BAN (Burrows-Abadi-Needham) logic. Furthermore, a comparison was drawn between the proposed protocol and the existing similar protocols in terms of performance evaluation. The comparison will reveal that the proposed protocol is both lightweight and highly secure.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"17 3-4","pages":"209-223"},"PeriodicalIF":1.2,"publicationDate":"2023-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12064","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50132670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Research on mapping recognition of arc welding molten pool characterisation and penetration state based on embedded system","authors":"Yanjun Zhu,&nbsp;Zhisheng Wu,&nbsp;Cuirong Liu","doi":"10.1049/cdt2.12055","DOIUrl":"https://doi.org/10.1049/cdt2.12055","url":null,"abstract":"<p>In order to explore the mapping recognition of arc welding molten pool characterisation and penetration state, according to the idea of embedded system construction, this article adopts the idea of software and hardware co-design to find the zero-crossing point of the second derivative in welding image edge detection, and give a threshold. When the absolute value of the first-order derivative exceeds the threshold and has a different sign with the first-order derivative of the previous edge, it is judged as a valid edge. The welding current adopts a symmetrical pulsed AC square wave, and the proportion of heat flow input is high. At the base current, the arc light is darker, so a clear image is obtained. This article designs a simulation experiment to verify the effect of the embedded system in this article. From the experimental research, it can be known that the embedded system constructed in this article can play a certain role in the mapping recognition of the arc welding molten pool characterisation and penetration state.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"17 3-4","pages":"100-110"},"PeriodicalIF":1.2,"publicationDate":"2023-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12055","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50145571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel self-timing CMOS first-edge take-all circuit for on-chip communication systems","authors":"Saleh Abdelhafeez,&nbsp;Shadi M. S. Harb","doi":"10.1049/cdt2.12059","DOIUrl":"https://doi.org/10.1049/cdt2.12059","url":null,"abstract":"<p>In today's communication systems, it has become prominent for processing elements (PEs) to receive requests with simultaneous, conflicting signals, which are unpredicted and randomly triggered. In such a case, multiple overlapping signal requests can potentially compete in the same PE causing erroneous operations or a halt of the communication cycle. The authors propose a self-timing CMOS first-edge take-all (FETA) circuit architecture, which examines two overlapping signals’ requests, and outputs only the leading-edge signal while the lagging-edge signal's request is declined. The FETA circuit functionality is considered as an essential component in First-In-First-Out for metastability avoidance, which usually occurs between the write and read overlapping requests for applications related to Internet of Things, Network-on-Chips, and microprocessor memory management units. HSPICE simulations for a 90 nm CMOS technology are used to verify the speed up to 1 GHz. Besides, the achievable resolution is in the order of 20 ps considering process variation sensitivity based on design inheriting symmetric timing paths between the two signals. Additionally, the proposed circuit architecture adopts a self-timing scheme obviating the overhead synchronisation circuitry, which comprises 12 D-Type Flip-Flops with about 300 transistors. This design is suited for HDL synthesis and FPGA application features.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"17 3-4","pages":"141-148"},"PeriodicalIF":1.2,"publicationDate":"2023-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12059","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50139916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An integrated taxonomy of standard indicators for ranking and selecting supercomputers","authors":"Davood Maleki,&nbsp;Alireza Mansouri,&nbsp;Ehsan Arianyan","doi":"10.1049/cdt2.12061","DOIUrl":"https://doi.org/10.1049/cdt2.12061","url":null,"abstract":"<p>Due to the ever-increasing computing requirements of modern applications, supercomputers are at the centre of attraction as a platform for high-performance computing. Although various features and indicators for testing and evaluating supercomputers are proposed in the literature, a comprehensive feature set to guide designers in comparing supercomputers and selecting an appropriate choice is not provided. Here, an integrated feature-based taxonomy comprised of seven indicator groups including passive infrastructure, hardware, software, support and maintenance, service, business, and security features is proposed. Also, a case study using our proposed framework is provided and a comparison between some commercial and research supercomputers including Fugaku's ideal supercomputer, Sharif supercomputer, Aramco supercomputer, and ITU supercomputer is presented. Moreover, here, the authors’ proposed method is compared with the Top500 method, which shows that the authors’ proposed method facilitates the ranking, comparison, and selection of the appropriate supercomputer in various fields by considering various aspects of design and implementation. The ranking results show that Aramco supercomputer, ITU supercomputer, and Sharif supercomputer have 65.9%, 57.6%, and 48.2% of ideal supercomputer points, respectively.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"17 3-4","pages":"162-179"},"PeriodicalIF":1.2,"publicationDate":"2023-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12061","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50139238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Compressing fully connected layers of deep neural networks using permuted features","authors":"Dara Nagaraju,&nbsp;Nitin Chandrachoodan","doi":"10.1049/cdt2.12060","DOIUrl":"https://doi.org/10.1049/cdt2.12060","url":null,"abstract":"<p>Modern deep neural networks typically have some fully connected layers at the final classification stages. These stages have large memory requirements that can be expensive on resource-constrained embedded devices and also consume significant energy just to read the parameters from external memory into the processing chip. The authors show that the weights in such layers can be modelled as permutations of a common sequence with minimal impact on recognition accuracy. This allows the storage requirements of FC layer(s) to be significantly reduced, which reflects in the reduction of total network parameters from 1.3× to 36× with a median of 4.45× on several benchmark networks. The authors compare the results with existing pruning, bitwidth reduction, and deep compression techniques and show the superior compression that can be achieved with this method. The authors also showed 7× reduction of parameters on VGG16 architecture with ImageNet dataset. The authors also showed that the proposed method can be used in the classification stage of the transfer learning networks.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"17 3-4","pages":"149-161"},"PeriodicalIF":1.2,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12060","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50149530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Verification of serialising instructions for security against transient execution attacks","authors":"Kushal K. Ponugoti,&nbsp;Sudarshan K. Srinivasan,&nbsp;Nimish Mathure","doi":"10.1049/cdt2.12058","DOIUrl":"https://doi.org/10.1049/cdt2.12058","url":null,"abstract":"<p>Transient execution attacks such as Spectre and Meltdown exploit speculative execution in modern microprocessors to leak information via cache side-channels. Software solutions to defend against many transient execution attacks employ the <i>lfence</i> serialising instruction, which does not allow instructions that come after the <i>lfence</i> to execute out-of-order with respect to instructions that come before the <i>lfence</i>. However, errors and Trojans in the hardware implementation of <i>lfence</i> can be exploited to compromise the software mitigations that use <i>lfence</i>. The aforementioned security gap has not been identified and addressed previously. The authors provide a formal method solution that addresses the verification of <i>lfence</i> hardware implementation. The authors also show how hardware Trojans can be designed to circumvent <i>lfence</i> and demonstrate that their verification approach will flag such Trojans as well. The authors have demonstrated the efficacy of our approach using RSD, which is an open source RISC-V based superscalar out-of-order processor.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"17 3-4","pages":"127-140"},"PeriodicalIF":1.2,"publicationDate":"2023-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12058","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50147574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}