International Journal of Numerical Modelling-Electronic Networks Devices and Fields最新文献

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Design and Analysis of Microstrip Line Fed Gap Coupled Triple Band Slotted Patch Antenna for WiMAX, WLAN, and Sub-6 GHz 5G Applications 用于WiMAX、WLAN和Sub-6 GHz 5G应用的微带线馈隙耦合三带开槽贴片天线设计与分析
IF 1.6 4区 工程技术
Ramesh Kumar Verma, Vikram Bali, Akhilesh Kumar, Prabina Pattanayak, Ravi Kant Prasad, Maninder Singh
{"title":"Design and Analysis of Microstrip Line Fed Gap Coupled Triple Band Slotted Patch Antenna for WiMAX, WLAN, and Sub-6 GHz 5G Applications","authors":"Ramesh Kumar Verma,&nbsp;Vikram Bali,&nbsp;Akhilesh Kumar,&nbsp;Prabina Pattanayak,&nbsp;Ravi Kant Prasad,&nbsp;Maninder Singh","doi":"10.1002/jnm.70005","DOIUrl":"https://doi.org/10.1002/jnm.70005","url":null,"abstract":"<div>\u0000 \u0000 <p>This paper presents a gap coupled triple band slot loaded microstrip patch antenna with parasitic patches. It consist inverted U-shape and inverted T-shape open-ended slots along with a rectangular slot at center of patch. The inverted U-shape open-ended slot generates a driven patch at bottom side and an inverted U-shape parasitic patch at middle side of patch while inverted T-shape open-ended slot generates two rectangular shape parasitic patches of same dimension at top side of patch. The proposed gap coupled antenna covers 2.29 to 2.77 GHz in first band, 3.25 to 3.65 GHz in second band and 4.67 to 5.72 GHz in third band with return losses of −23.2, −19.90, and −38.06 dB, respectively. The proposed antenna resonates at 2.57, 3.48, and 5.37 GHz with fractional bandwidth of 18.97% (480 MHz), 11.59% (400 MHz), and 20.21% (1050 MHz), respectively. The return loss and bandwidth of presented antenna is increases gradually by loading inverted U-shape and inverted T-shape open-ended slots along with a rectangular slot in antenna patch. The proposed antenna exhibits stable peak gain of 4.45, 4.81, and 5.26 dBi and efficiency of 89.5%, 89%, and 90% in three resonating bands. The antenna resonating bands are applicable for WiMAX: 2.5/3.5/5.5 GHz (2.5–2.69, 3.4–3.69, and 5.25–5.85 GHz), WLAN: 2.4/5.2 GHz (2.4–2.484 and 5.15–5.35 GHz) and sub-6 GHz 5G: 3.5 GHz (3.3–3.8 GHz). The size of antenna is 40 mm × 50 mm (0.34 × <span></span><math>\u0000 <semantics>\u0000 <mrow>\u0000 <msubsup>\u0000 <mrow>\u0000 <mn>0.43</mn>\u0000 <mi>λ</mi>\u0000 </mrow>\u0000 <mn>0</mn>\u0000 <mn>2</mn>\u0000 </msubsup>\u0000 </mrow>\u0000 <annotation>$$ 0.43{lambda}_0^2 $$</annotation>\u0000 </semantics></math> at frequency 2.57 GHz). The gap coupled antenna geometry is fed by microstrip line feed and simulated by IE3D simulation tool.</p>\u0000 </div>","PeriodicalId":50300,"journal":{"name":"International Journal of Numerical Modelling-Electronic Networks Devices and Fields","volume":"37 6","pages":""},"PeriodicalIF":1.6,"publicationDate":"2024-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142860958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Enhancing FeFET Structures for Non-Volatile On-Chip Memories: Design and Comparative Analysis 增强非易失性片上存储器的ffet结构:设计与比较分析
IF 1.6 4区 工程技术
Mandeep Singh, Tarun Chaudhary, Balwinder Raj
{"title":"Enhancing FeFET Structures for Non-Volatile On-Chip Memories: Design and Comparative Analysis","authors":"Mandeep Singh,&nbsp;Tarun Chaudhary,&nbsp;Balwinder Raj","doi":"10.1002/jnm.70004","DOIUrl":"https://doi.org/10.1002/jnm.70004","url":null,"abstract":"<div>\u0000 \u0000 <p>FeFET architectures for non-volatile on-chip memory are designed and compared in this investigation study. Because of its inherent non-volatile properties and low power requirements, FeFETs are attracting a lot of interest as prospective candidates for future memory technology. The aim of this paper is to investigate several FeFET designs and assess how well they function in terms of important factors including durability, retention, speed, and endurance. Using device simulations and experimental data, a number of FeFET architectures, such as MFS, MFIS, MFMIS, and MF-ABO<sub>3</sub>, are analyzed and contrasted. Comparative study gives light on the advantages and disadvantages of various FeFET architectures; improving our comprehension of how well-suited they are for non-volatile on-chip memory. This work will contribute to the improvement of FeFET devices for upcoming integrated circuits and progress the development of sophisticated FeFET-based memory techniques.</p>\u0000 </div>","PeriodicalId":50300,"journal":{"name":"International Journal of Numerical Modelling-Electronic Networks Devices and Fields","volume":"37 6","pages":""},"PeriodicalIF":1.6,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142859966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SG-FET Based Spiking Neuron With Ultra-Low Energy Consumption for ECG Signal Classification 基于SG-FET的超低能耗尖峰神经元心电信号分类
IF 1.6 4区 工程技术
Babar M. Zargar, Mudasir A. Khanday, Farooq A. Khanday
{"title":"SG-FET Based Spiking Neuron With Ultra-Low Energy Consumption for ECG Signal Classification","authors":"Babar M. Zargar,&nbsp;Mudasir A. Khanday,&nbsp;Farooq A. Khanday","doi":"10.1002/jnm.70003","DOIUrl":"https://doi.org/10.1002/jnm.70003","url":null,"abstract":"<div>\u0000 \u0000 <p>This paper presents an energy-efficient single-transistor leaky integrate-and-fire neuron, based on Suspended Gate-FET (SG-FET), for signal classification and neuromorphic computing applications. By leveraging the SG-FET model, extensive simulations were conducted to demonstrate the device's remarkable neuronal ability. The device faithfully emulated the intricate behaviour of biological neurons, without the need for external circuitry. One of the standout achievements lies in the device's astonishingly low energy consumption of 94.5 aJ per spike. Therefore, it outperforms the previously proposed one-transistor (1-T) neurons, which makes it a potential candidate for energy-efficient neuromorphic computing. To verify the practical viability of the device, an emulation was seamlessly integrated into a spiking neural network framework, allowing for real-time signal classification. In this specific case, the device excelled in the classification of electrocardiogram (ECG) signals, achieving an impressive accuracy rate of 85.6%. This outcome highlights the device's efficacy in handling real-world signal processing tasks with remarkable precision and efficiency.</p>\u0000 </div>","PeriodicalId":50300,"journal":{"name":"International Journal of Numerical Modelling-Electronic Networks Devices and Fields","volume":"37 6","pages":""},"PeriodicalIF":1.6,"publicationDate":"2024-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142762442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A FinFET-Based Low-Power Static Random Access Memory Cell With Improved Stability 一种基于finfet的低功耗静态随机存取存储单元
IF 1.6 4区 工程技术
Gautam Rana, Ashish Sachdeva, M. Elangovan, Kulbhushan Sharma
{"title":"A FinFET-Based Low-Power Static Random Access Memory Cell With Improved Stability","authors":"Gautam Rana,&nbsp;Ashish Sachdeva,&nbsp;M. Elangovan,&nbsp;Kulbhushan Sharma","doi":"10.1002/jnm.70002","DOIUrl":"https://doi.org/10.1002/jnm.70002","url":null,"abstract":"<div>\u0000 \u0000 <p>This work presents a FinFET-based stable, and low-power consuming static random access memory (SRAM) bit-cell that used eight transistors. The performance parameter of proposed feedback-cutting 8T (FC8T) is compared with four pre-published cell circuits, i.e., 6T, read-decoupled 8T(8TRD), Schmitt-trigger based 10T (10TST), and Schmitt-trigger-based modified 10 T (10TMST). The write power in proposed design is reduced by 1.36×/1.32×/1.88×/1.47× compared to 6T/8TRD/10TST/10TMST cells. The write and read stability of proposed design is improved by 1.15×/1.86×/1.28×/1.148× and 2.27×/1×/1.57×/1.11×, respectively. The proposed design also shows the low variability compared to other SRAM bit-cells.</p>\u0000 </div>","PeriodicalId":50300,"journal":{"name":"International Journal of Numerical Modelling-Electronic Networks Devices and Fields","volume":"37 6","pages":""},"PeriodicalIF":1.6,"publicationDate":"2024-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142749190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Accelerated Characteristic Mode Calculation for PEC Objects Using ACA-QR-SVD Algorithm 使用 ACA-QR-SVD 算法加速 PEC 物体的特征模式计算
IF 1.6 4区 工程技术
Pengfei Zhang, Shaode Huang, Jiejun Zhang, Jianhua Zhou, Tao Hong
{"title":"Accelerated Characteristic Mode Calculation for PEC Objects Using ACA-QR-SVD Algorithm","authors":"Pengfei Zhang,&nbsp;Shaode Huang,&nbsp;Jiejun Zhang,&nbsp;Jianhua Zhou,&nbsp;Tao Hong","doi":"10.1002/jnm.3313","DOIUrl":"https://doi.org/10.1002/jnm.3313","url":null,"abstract":"<div>\u0000 \u0000 <p>Characteristic mode (CM) analysis serves as a powerful tool for evaluating the radiation and scattering characteristics of objects. CM formulations within the method of moments (MoM) framework are widely favored due to their ability to offer clear physical insights, handle complex shapes, and facilitate straightforward implementation. However, MoM-based CM formulations become inefficient when applied to electrically large objects due to the dense matrices involved. This article introduces a novel approach using a fast low-rank decomposition-based implicitly restarted Arnoldi method (IRAM) to accelerate CM computations. The adaptive cross approximation (ACA) and QR-SVD algorithms are employed to efficiently compute the low-rank decomposition of matrices. The ACA-QR-SVD algorithm offers advantages in matrix filling, LU factorization, and matrix–vector multiplication processes, thereby enhancing efficiency. Numerical simulations on two representative objects demonstrate that the proposed algorithm notably improves computational speed and reduces memory requirements while maintaining high computational accuracy.</p>\u0000 </div>","PeriodicalId":50300,"journal":{"name":"International Journal of Numerical Modelling-Electronic Networks Devices and Fields","volume":"37 6","pages":""},"PeriodicalIF":1.6,"publicationDate":"2024-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142707871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Enhanced Performance of Dual Material Double Gate Negative Capacitance Tunnel Field Effect Transistor (DMDG-NC-TFET) via HZO Ferroelectric Integration for Improved Drain Current and Subthreshold Swing 通过 HZO 铁电集成提高漏极电流和次阈值摆幅的双材料双栅负电容隧道场效应晶体管 (DMDG-NC-TFET) 性能
IF 1.6 4区 工程技术
P. Hannah Blessy, A. Shenbagavalli, T. S. Arun Samuel, J. Charles Pravin
{"title":"Enhanced Performance of Dual Material Double Gate Negative Capacitance Tunnel Field Effect Transistor (DMDG-NC-TFET) via HZO Ferroelectric Integration for Improved Drain Current and Subthreshold Swing","authors":"P. Hannah Blessy,&nbsp;A. Shenbagavalli,&nbsp;T. S. Arun Samuel,&nbsp;J. Charles Pravin","doi":"10.1002/jnm.70001","DOIUrl":"https://doi.org/10.1002/jnm.70001","url":null,"abstract":"<div>\u0000 \u0000 <p>This paper developed the novel structure of a dual material double gate negative capacitance tunnel field effect transistor (DMDG-NC-TFET) using HZO ferroelectric material. This study systematically improved the drain current and subthreshold swing (SS) by inducing a negative capacitance effect in a gate stack. The proposed gate oxide structure is a stack configuration of ferroelectric material, and high-k dielectric to improve gate control. The Landau–Khalatnikov (LK) equation is used to solve the Poisson equation and get an accurate estimate of the channel potential. Kane's model is used for band-to-band generation rate calculation. For modelling the drain current, the band-to-band tunnelling (G<sub>btbt</sub>) generation rate is integrated using the entire device volume. The impact of varying ferroelectric thickness in the proposed structure has been investigated with the simulated results. The outcomes demonstrate that the device can obtain better improvements in ON current and SS, compared to conventional DMDG-TFET. By contrasting the analytical results with the outcomes of the TCAD simulation, the effectiveness of the proposed methodology has been demonstrated.</p>\u0000 </div>","PeriodicalId":50300,"journal":{"name":"International Journal of Numerical Modelling-Electronic Networks Devices and Fields","volume":"37 6","pages":""},"PeriodicalIF":1.6,"publicationDate":"2024-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142707719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
EEG Emotion Recognition Based on GADF and AMB-CNN Model 基于 GADF 和 AMB-CNN 模型的脑电图情感识别
IF 1.6 4区 工程技术
Qian Zhao, Dandan Zhao, Wuliang Yin
{"title":"EEG Emotion Recognition Based on GADF and AMB-CNN Model","authors":"Qian Zhao,&nbsp;Dandan Zhao,&nbsp;Wuliang Yin","doi":"10.1002/jnm.70000","DOIUrl":"10.1002/jnm.70000","url":null,"abstract":"<div>\u0000 \u0000 <p>Deep learning has achieved better results in natural language processing, computer vision, and other fields. Nowadays, more deep learning algorithms have also been applied in brain-based emotion recognition. In the studies on brain-based emotion recognition, deep learning models typically use one-dimensional time series as the input and cannot fully leverage the advantages of the models in image classification or recognition. To address this issue, based on the publicly available SEED and DEAP datasets, the Gramian angular difference field (GADF) method was proposed to construct two-dimensional image representation datasets: SEED-GADF and DEAP-GADF datasets, in the paper. Additionally, a convolutional attention mechanism model (AMB-CNN) was introduced and its classification performance was validated on SEED-GADF and DEAP-GADF datasets. AMB-CNN achieved an average accuracy of 90.8%, a recall rate of 90%, and AUC of 96.86% on SEED-GADF. On DEAP-GADF, the average accuracy, recall rate, and AUC respectively reached 96.06%, 96.06%, and 98.58% in the valence dimension and 96.11%, 96.11%, and 98.73% in the arousal dimension. Finally, the comparison results with various algorithms and ablation experiments proved the superiority of the proposed model.</p>\u0000 </div>","PeriodicalId":50300,"journal":{"name":"International Journal of Numerical Modelling-Electronic Networks Devices and Fields","volume":"37 6","pages":""},"PeriodicalIF":1.6,"publicationDate":"2024-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142665595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A High Power Density Ku-Band GaN Power Amplifier Based on Device-Level Thermal Analysis 基于器件级热分析的高功率密度 Ku 波段氮化镓功率放大器
IF 1.6 4区 工程技术
Jiuding Zhou, Chupeng Yi, Wenliang Liu, Yang Lu, Xiaohua Ma, Yuanfu Zhao, Yue Hao
{"title":"A High Power Density Ku-Band GaN Power Amplifier Based on Device-Level Thermal Analysis","authors":"Jiuding Zhou,&nbsp;Chupeng Yi,&nbsp;Wenliang Liu,&nbsp;Yang Lu,&nbsp;Xiaohua Ma,&nbsp;Yuanfu Zhao,&nbsp;Yue Hao","doi":"10.1002/jnm.3311","DOIUrl":"https://doi.org/10.1002/jnm.3311","url":null,"abstract":"<div>\u0000 \u0000 <p>This paper introduces a new design method for a high-power density GaN MMIC amplifier operating in the Ku-band. A thermal model to investigate the thermal distribution of power amplifiers is proposed to achieve optimal performance in terms of power density, chip size, and channel temperature. The thermal distribution and channel temperature of a single device, an eight-way parallel device combination, and the entire PA layout are obtained by finite element simulation. The thermal coupling effects of high-power MMICs are analyzed in detail. The thermal resistances are extracted from the simulation to design a Ku-band amplifier. Measurement results demonstrate that the designed amplifier achieves 43.0–44.2 dBm output power and 22.7%–34.5% PAE at 28 V drain voltage with a 100 μs pulse width and 10% duty cycle within 12–18 GHz. The proposed design method enables the amplifier to have a compact layout of 10.88 mm<sup>2</sup> and a power density between 1.84 and 2.42 W/mm. This design method can offer valuable insights for future development of high-power MMIC amplifiers.</p>\u0000 </div>","PeriodicalId":50300,"journal":{"name":"International Journal of Numerical Modelling-Electronic Networks Devices and Fields","volume":"37 6","pages":""},"PeriodicalIF":1.6,"publicationDate":"2024-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142664798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
One-Step Leapfrog 3D Split-Field FDTD Method for Periodic Structures at Oblique Incidence 斜入射周期性结构的一步跃迁三维分场 FDTD 方法
IF 1.6 4区 工程技术
Lingpu Zhang, Juan Chen, Chunhui Mou, Ao Peng
{"title":"One-Step Leapfrog 3D Split-Field FDTD Method for Periodic Structures at Oblique Incidence","authors":"Lingpu Zhang,&nbsp;Juan Chen,&nbsp;Chunhui Mou,&nbsp;Ao Peng","doi":"10.1002/jnm.3315","DOIUrl":"https://doi.org/10.1002/jnm.3315","url":null,"abstract":"<div>\u0000 \u0000 <p>This article introduces a one-step leapfrog three-dimensional (3D) split-field finite-difference time-domain (SF-FDTD) method designed for analyzing periodic structures under oblique incidence, aiming to improve computational efficiency. Initially, it introduces new variables to substitute the field components postsplitting. After that, it applies time-centered approximate difference method to precisely adjust the time step for each iteration. It eliminates the need for empirical coefficients when performing calculations with lossy materials. Finally, it derives the implementation of the convolutional perfectly matched layer (CPML) for the proposed method. The proposed method is both easier to implement and more resource-efficient, significantly cutting down CPU usage and memory consumption. Numerical results confirm its improved efficiency.</p>\u0000 </div>","PeriodicalId":50300,"journal":{"name":"International Journal of Numerical Modelling-Electronic Networks Devices and Fields","volume":"37 6","pages":""},"PeriodicalIF":1.6,"publicationDate":"2024-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142664802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Static Approximate Modified Mirror—Full Adder for High Speed and Low Power Operations Using 32 nm CNTFET Technology 利用 32 纳米 CNTFET 技术实现高速低功耗运行的静态近似修正镜像满加法器
IF 1.6 4区 工程技术
Sagar Juneja, M. Elangovan, Kulbhushan Sharma
{"title":"Static Approximate Modified Mirror—Full Adder for High Speed and Low Power Operations Using 32 nm CNTFET Technology","authors":"Sagar Juneja,&nbsp;M. Elangovan,&nbsp;Kulbhushan Sharma","doi":"10.1002/jnm.3320","DOIUrl":"https://doi.org/10.1002/jnm.3320","url":null,"abstract":"<div>\u0000 \u0000 <p>The error tolerance nature of the digital multimedia applications enables the implementation of approximate digital circuits to achieve the benefits of high speed of operation and low power consumption. This paper proposes a static approximate modified mirror full adder (SAMM-FA) circuit designed using logic level approximation to reduce the number of transistors in the circuit. Owing to the balanced electrical characteristics, better stability and higher on-current to off-current ratio (<i>I</i><sub>on</sub>/<i>I</i><sub>off</sub>), 32 nm carbon nanotube field effect transistor (CNTFET) technology has been used for implementing the proposed circuit in the Cadence Virtuoso tool. Featuring only 10 transistors and operating at a supply voltage of 0.5 V, the proposed SAMM-FA has a low power dissipation of just 4.14 nW, and propagation delay of just 3.82 ps. The power delay product and energy delay product figure of merits of the proposed circuit are found to be excellent when compared with the contemporary designs.</p>\u0000 </div>","PeriodicalId":50300,"journal":{"name":"International Journal of Numerical Modelling-Electronic Networks Devices and Fields","volume":"37 6","pages":""},"PeriodicalIF":1.6,"publicationDate":"2024-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142664930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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