International Journal of Numerical Modelling-Electronic Networks Devices and Fields最新文献

{"title":"Design and Performance Analysis of Walrus Optimization Algorithm (WaOA)-Based Cascade Controller for Load Frequency Control of a Multi-Area Power System With Renewable Sources","authors":"Jahanzeab Hussain,&nbsp;Runmin Zou,&nbsp;Zhenlong Wu,&nbsp;Pawan Kumar Pathak,&nbsp;Samina Akhtar","doi":"10.1002/jnm.70046","DOIUrl":"https://doi.org/10.1002/jnm.70046","url":null,"abstract":"<div>\u0000 \u0000 <p>One of the key challenges in interconnected power systems is developing an effective control strategy to mitigate frequency and power deviations caused by the intermittency of renewable energy sources (RESs) and varying load demands. This research introduces an innovative cascade control strategy featuring a PPD controller followed by a PI controller (PPD-PI) for load frequency control (LFC) in a two-area power system with photovoltaic (PV), wind, and thermal reheat power sources. The walrus optimization algorithm (WaOA) is employed to fine-tune the parameters of both the PIDn and PPD-PI controllers, with the goal of minimizing the integral time absolute error (ITAE). The study first applies the WaOA-tuned PID with filter (PIDn) controller to showcase WaOA's effectiveness in LFC, achieving the lowest objective function value of 0.3862, surpassing MFO (0.3921) and GA (0.4127). The robustness of the WaOA-tuned PPD-PI controller is then evaluated under various conditions, including step load disturbances, random load patterns, and parameter uncertainties. The proposed controller achieves significant improvements, with a 36.8% reduction in ITAE compared to the second-best CGO-tuned PIDn-PI controller in Case 2, and a 54.45% reduction in ITAE compared to the second-best COA-tuned PDn-PI controller in Case 3. To further highlight the advantages of the proposed scheme, the analysis also includes nonlinearities such as governor dead band (GDB), boiler dynamics (BD), and generation rate constraints (GRC), along with sensitivity analysis and stability testing under a <span></span><math>\u0000 <semantics>\u0000 <mrow>\u0000 <mo>±</mo>\u0000 <mn>25</mn>\u0000 <mo>%</mo>\u0000 </mrow>\u0000 <annotation>$$ pm 25% $$</annotation>\u0000 </semantics></math> change in system parameters. The results strongly demonstrate the superior performance of the WaOA-optimized PPD-PI controller over existing methods.</p>\u0000 </div>","PeriodicalId":50300,"journal":{"name":"International Journal of Numerical Modelling-Electronic Networks Devices and Fields","volume":"38 2","pages":""},"PeriodicalIF":1.6,"publicationDate":"2025-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143793408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Lateral Si/Si1-xGex/Si Channel Heterostructure Charge Plasma Nanowire JLFET to Eliminate the Effects of Variation of Geometrical Dimensions","authors":"Anchal Thakur,&nbsp;Prashant Mani,&nbsp;Prabin Kumar Bera,&nbsp;Nishant Srivastava,&nbsp;Girish Wadhwa,&nbsp;Antonino Proto","doi":"10.1002/jnm.70042","DOIUrl":"https://doi.org/10.1002/jnm.70042","url":null,"abstract":"<div>\u0000 \u0000 <p>In this article, a charge plasma (CP) based doping-less (DL) nanowire junctionless field effect transistor (NW JLFET) has been investigated for better immunity against geometrical dimension variation from a low power application perspective. SiGe source/drain and Si/SiGe/Si heterostructure channel have been used to improve the electrostatics in the channel to reduce the leakage current. With this doping-less structure, the concept of charge plasmas has been incorporated by selecting electrodes with appropriate work functions. In addition to a low thermal budget, the doping-less devices are easier to fabricate, have a reduced random fluctuation effect, and offer a low cost per unit. The doping-less structure also offers improved mobility and higher current flow. The proposed device is compared with the conventional SiGe nanowire junctionless FET. When both devices are compared, lateral Si/SiGe/Si CP DL NW JLFET shows fewer changes in geometrical dimension variation in terms of germanium content <i>x</i>, nanowire thickness (<i>t</i>_si) and doping profile (<i>N</i>_d) on the drain current (<i>I</i>_DS), <i>I</i>_ON/<i>I</i>_OFF ratio, threshold voltage (<i>V</i>th), drain-induced barrier lowering (DIBL), and subthreshold slope (SS). A drain current model for lateral Si/SiGe/Si CP DL NW JLFET has also been developed in this paper, which includes the impact of the charge plasma technique. The impact of geometrical dimension variation on the analog characteristics of both devices has been studied in terms of like transconductance (<i>g</i>_m) and transconductance gain factor (TGF) (<i>g</i>_m/<i>I</i>_DS). Thus, in the lateral Si/SiGe/Si CP DL NW JLFET, the charge plasma technique along with channel engineering solves the problem of geometrical dimension variation without affecting the inherited properties of junctionless devices.</p>\u0000 </div>","PeriodicalId":50300,"journal":{"name":"International Journal of Numerical Modelling-Electronic Networks Devices and Fields","volume":"38 2","pages":""},"PeriodicalIF":1.6,"publicationDate":"2025-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143793407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Triple RESURF Si/SiC HeteroJunction LDMOS and Its Analytical Model","authors":"Nan Wang,&nbsp;Xiarong Hu,&nbsp;Yonggen Xu,&nbsp;Tianci Li","doi":"10.1002/jnm.70039","DOIUrl":"https://doi.org/10.1002/jnm.70039","url":null,"abstract":"<div>\u0000 \u0000 <p>In this paper, a Triple RESURF Si/SiC HeteroJunction LDMOS (TR-HJ-LDMOS) structure is proposed. The TR-HJ-LDMOS features a P-type layer buried deep into the drift region. Compared with Double RESURF (DR) and Single RESURF (SR) Si/SiC HeteroJunction LDMOS (HJ-LDMOS), the drift depletion effect is strengthened. As a result, the drift doping concentration is increased, and the specific on-resistance (<i>R</i>_s,on) is decreased. The simulation results show that the <i>R</i>_s,on of the 300 V-class TR-HJ-LDMOS is 20mΩ·cm², which is reduced by 28.6% and 50.0%, respectively, compared with DR-HJ-LDMOS and SR-HJ-LDMOS. Moreover, an analytical model for the electric field distributions of the Triple RESURF Si/SiC HeteroJunction LDMOS is proposed in this paper. The analytical expressions of the surface field and potential distributions are presented. The effect of the P-layer concentration, thickness, position, as well as the drain depth and drift thickness on the electric field distributions of the TR-HJ-LDMOS are discussed in detail. The proposed model can also be applied in the SR and DR HJ-LDMOS.</p>\u0000 </div>","PeriodicalId":50300,"journal":{"name":"International Journal of Numerical Modelling-Electronic Networks Devices and Fields","volume":"38 2","pages":""},"PeriodicalIF":1.6,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143749774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"FDTD Simulation for Optimization of 3D Two-Layered Au Nanocone SERS Substrates","authors":"Songya Cui,&nbsp;Dongxue Han,&nbsp;Guang Chen,&nbsp;Yufeng Yu,&nbsp;Liang Peng","doi":"10.1002/jnm.70048","DOIUrl":"https://doi.org/10.1002/jnm.70048","url":null,"abstract":"<div>\u0000 \u0000 <p>Surface-enhanced Raman spectroscopy has emerged as a powerful tool for molecular detection, with 3D-nanostructured substrates offering significant advantages in sensitivity enhancement and reproducibility. In this study, finite-difference time-domain methods were performed to optimize the design of 3D two-layered Au nanocone SERS substrates. The electric (E) field distribution and enhancement were systematically analyzed for different nanocone configurations, including variations in the number of nanocones per layer. The results demonstrate that these substrates significantly amplify the E-field intensity, primarily due to multiple plasmon coupling modes. Notably, the E-field strength is approximately 1.5 times higher than that of the single primary Au nanocones. Furthermore, the simulations reveal that E hot spots are predominantly localized at the tips of the nanocones, where the highest field intensities are observed. These findings provide valuable insights for the rational design of high-performance 3D SERS substrates and highlight the potential of two-layered Au nanocone arrays for advanced molecular sensing applications.</p>\u0000 </div>","PeriodicalId":50300,"journal":{"name":"International Journal of Numerical Modelling-Electronic Networks Devices and Fields","volume":"38 2","pages":""},"PeriodicalIF":1.6,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143749854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Comprehensive Threshold Voltage Model for Si-Based MOSFETs From Room to Cryogenic Temperatures","authors":"Yijie Zhang,&nbsp;XinYi Zhang,&nbsp;Guohe Zhang,&nbsp;Daofeng Zhang,&nbsp;Bo Li,&nbsp;Lei Wang,&nbsp;Jianhui Bu","doi":"10.1002/jnm.70041","DOIUrl":"https://doi.org/10.1002/jnm.70041","url":null,"abstract":"<div>\u0000 \u0000 <p>This study analyses various factors that affect the threshold voltage of MOSFETs at deep cryogenic temperatures, including band-tail state, field-assisted ionization, and interface traps. Based on the analysis, a new model is developed for Si-based MOSFETs covering a wide temperature range from 10 to 300 K. The validity of the model is confirmed through experiments of bulk silicon MOSFETs, FDSOI MOSFETs, and n-FinFET.</p>\u0000 </div>","PeriodicalId":50300,"journal":{"name":"International Journal of Numerical Modelling-Electronic Networks Devices and Fields","volume":"38 2","pages":""},"PeriodicalIF":1.6,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143749620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Novel Approach to Solve Nonlinear Higher Order Fractional Volterra–Fredholm Integro-Differential Equations Using Laplace Adomian Decomposition Method","authors":"Maha M. Hamood,&nbsp;Abdulrahman A. Sharif,&nbsp;Kirtiwant P. Ghadle","doi":"10.1002/jnm.70040","DOIUrl":"https://doi.org/10.1002/jnm.70040","url":null,"abstract":"<div>\u0000 \u0000 <p>This research will integrate the Laplace transform method with the Adomian Decomposition Method to semi-analytically treat nonlinear integro-fractional differential equations of the Volterra–Fredholm–Hammerstein type. The higher-order fractional derivative will be expressed in the Caputo sense, and the first-order simple degenerate and the difference kernel will be used. With this approach, the inverse Laplace transform is applied, and the solution of the equation is viewed as the sum of an endless series of components that usually converge to the solution. Numerical applications frequently employ a shortened number of terms when a closed-form solution is not possible. Lastly, a diagram displaying the arrived at and discussed solutions was shown along with illustrative examples.</p>\u0000 </div>","PeriodicalId":50300,"journal":{"name":"International Journal of Numerical Modelling-Electronic Networks Devices and Fields","volume":"38 2","pages":""},"PeriodicalIF":1.6,"publicationDate":"2025-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143741470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Affine Linear Solution of the Nonlinear Inverse Power Flow Problem in Resistive Networks","authors":"Martin Wachs,&nbsp;Miriam Primbs","doi":"10.1002/jnm.70026","DOIUrl":"https://doi.org/10.1002/jnm.70026","url":null,"abstract":"&lt;p&gt;In the analysis of linear electrical networks, an inverse problem can be inferring all edge impedances only from known external voltage sources and measured resulting edge currents. Given all external edge voltages &lt;span&gt;&lt;/span&gt;&lt;math&gt;\u0000 &lt;semantics&gt;\u0000 &lt;mrow&gt;\u0000 &lt;msub&gt;\u0000 &lt;mi&gt;u&lt;/mi&gt;\u0000 &lt;mi&gt;ext&lt;/mi&gt;\u0000 &lt;/msub&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;annotation&gt;$$ {boldsymbol{u}}_{mathrm{ext}} $$&lt;/annotation&gt;\u0000 &lt;/semantics&gt;&lt;/math&gt; and all resulting edge currents &lt;span&gt;&lt;/span&gt;&lt;math&gt;\u0000 &lt;semantics&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mi&gt;i&lt;/mi&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;annotation&gt;$$ boldsymbol{i} $$&lt;/annotation&gt;\u0000 &lt;/semantics&gt;&lt;/math&gt;, we present a new calculation method for the edge resistances &lt;span&gt;&lt;/span&gt;&lt;math&gt;\u0000 &lt;semantics&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mi&gt;R&lt;/mi&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;annotation&gt;$$ boldsymbol{R} $$&lt;/annotation&gt;\u0000 &lt;/semantics&gt;&lt;/math&gt;, with the assumption that the reactance is everywhere zero (e.g., a resistive network). Our considerations are based on affine subspaces and their intersection. We show, that in case of having a sequence of &lt;span&gt;&lt;/span&gt;&lt;math&gt;\u0000 &lt;semantics&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mi&gt;l&lt;/mi&gt;\u0000 &lt;mo&gt;≥&lt;/mo&gt;\u0000 &lt;mn&gt;3&lt;/mn&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;annotation&gt;$$ lge 3 $$&lt;/annotation&gt;\u0000 &lt;/semantics&gt;&lt;/math&gt; measurements &lt;span&gt;&lt;/span&gt;&lt;math&gt;\u0000 &lt;semantics&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mfenced&gt;\u0000 &lt;msub&gt;\u0000 &lt;mi&gt;u&lt;/mi&gt;\u0000 &lt;msub&gt;\u0000 &lt;mi&gt;ext&lt;/mi&gt;\u0000 &lt;mn&gt;1&lt;/mn&gt;\u0000 &lt;/msub&gt;\u0000 &lt;/msub&gt;\u0000 &lt;msub&gt;\u0000 &lt;mi&gt;i&lt;/mi&gt;\u0000 &lt;mn&gt;1&lt;/mn&gt;\u0000 &lt;/msub&gt;\u0000 &lt;/mfenced&gt;\u0000 &lt;mo&gt;,&lt;/mo&gt;\u0000 &lt;mo&gt;…&lt;/mo&gt;\u0000 &lt;mo&gt;,&lt;/mo&gt;\u0000 &lt;mfenced&gt;\u0000 &lt;msub&gt;\u0000 &lt;mi&gt;u&lt;/mi&gt;\u0000 &lt;msub&gt;\u0000 &lt;mi&gt;ext&lt;/mi&gt;\u0000 &lt;mi&gt;l&lt;/mi&gt;\u0000 &lt;/msub&gt;\u0000 &lt;/msub&gt;\u0000 &lt;msub&gt;\u0000 &lt;mi&gt;i&lt;/mi&gt;\u0000 &lt;mi&gt;l&lt;/mi&gt;\u0000 &lt;/msub&gt;\u0000 &lt;/mfenced&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;annotation&gt;$$ left({boldsymbol{u}}_{{operatorname{ext}}_1},{boldsymbol{i}}_1right),dots, left({boldsymbol{u}}_{{operatorname{ext}}_l},{boldsymbol{i}}_lright) $$&lt;/annotation&gt;\u0000 &lt;/semantics&gt;&lt;/math&gt;, we can calculate &lt;span&gt;&lt;/span&gt;&lt;math&gt;\u0000 ","PeriodicalId":50300,"journal":{"name":"International Journal of Numerical Modelling-Electronic Networks Devices and Fields","volume":"38 2","pages":""},"PeriodicalIF":1.6,"publicationDate":"2025-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1002/jnm.70026","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143717360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"CNTFET Based Design of Optimized High Frequency VCII and Its Application as Mixed Mode Universal Filter Suitable for VHF Band","authors":"Smita Khole,&nbsp;Mousumi Bhanja,&nbsp;Mohammad Faseehuddin,&nbsp;Sadia Shireen,&nbsp;Worapong Tangsrirat","doi":"10.1002/jnm.70034","DOIUrl":"https://doi.org/10.1002/jnm.70034","url":null,"abstract":"<div>\u0000 \u0000 <p>In this research, Carbon Nanotube Field-effect Transistors (CNTFETs) are employed in the design of a second-generation Voltage Conveyor (VCII), an analog block. The aim of this research is to study CNTFETs as an alternative to CMOS for designing high-frequency and low-voltage circuits. The complete design procedure for VCII and its two variants, namely, modified VCII (M-VCII) and VCII minus (VCII−) is presented. This work incorporates variations in the design variables of CNTFETs, including pitch, the number of tubes, and the diameter of carbon nanotubes (CNT). The study explores the impact of these variations on the critical performance parameters of the CNTFETs. The optimal values of the design variables for each transistor are calculated through extensive simulation analysis using the Verilog-A semi-empirical Stanford Virtual-Source Carbon Nanotube Field-Effect Transistor model. The CNTFET-based VCII and its variants are optimized and validated at the supply voltage of ±0.9 V. The CNTFET-based VCII exhibits improved voltage and current bandwidths of 1.4 and 1 THz, respectively. The input/output impedance and power dissipation also validate improvement compared to CMOS implementation. To verify the performance of the proposed VCII and its variants, they are used in the design of a mixed-mode universal filter (MMUF). The proposed filter is designed for a cut-off frequency of 79 MHz and consumes 7.368 mW of power. The effects of parameter variations and noise on the VCII design are also discussed.</p>\u0000 </div>","PeriodicalId":50300,"journal":{"name":"International Journal of Numerical Modelling-Electronic Networks Devices and Fields","volume":"38 2","pages":""},"PeriodicalIF":1.6,"publicationDate":"2025-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143699018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Quasi-Vertical Diamond Schottky Barrier Diode With Sidewall-Enhanced n-Ga2O3/p-Diamond Junction Termination Extension","authors":"Chengwei Dong,&nbsp;Wang Lin,&nbsp;Tong Zhang,&nbsp;Xianyi Lv,&nbsp;Qiliang Wang,&nbsp;Liuan Li,&nbsp;Guangtian Zou","doi":"10.1002/jnm.70038","DOIUrl":"https://doi.org/10.1002/jnm.70038","url":null,"abstract":"<div>\u0000 \u0000 <p>In the present study, a quasi-vertical diamond Schottky barrier diode (SBD) with a junction termination extension (JTE) structure is designed and simulated using Silvaco software. We firstly investigate the influences of spatial location and thickness of the n-Ga₂O₃/p-diamond PN junction on the electrical performances. Subsequently, the doping concentration and width of the JTE region are optimized to achieve the highest Baliga Figure of Merit (BFOM) value, with the underlying mechanisms governing the electrical characteristics systematically analyzed. Furthermore, we also propose a sidewall-enhanced JTE structure to improve the breakdown voltage without influencing the on-resistance and turn-on voltage. In addition, it is found that the etching depth of the mesa presents minimal influence on the diamond SBD. These findings are beneficial to realizing a high-performance quasi-vertical diamond SBD.</p>\u0000 </div>","PeriodicalId":50300,"journal":{"name":"International Journal of Numerical Modelling-Electronic Networks Devices and Fields","volume":"38 2","pages":""},"PeriodicalIF":1.6,"publicationDate":"2025-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143690009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Machine Learning Based Modeling of Electrical Characteristics in Triangular Gate FinFETs for Low Power Electronics","authors":"M. Hemalatha,&nbsp;N. B. Balamurugan,&nbsp;M. Suguna,&nbsp;N. Ayyanar","doi":"10.1002/jnm.70036","DOIUrl":"https://doi.org/10.1002/jnm.70036","url":null,"abstract":"<div>\u0000 \u0000 <p>Modeling and optimization of devices play a critical role in the management of product quality and the advancement of technology within the industrial sector. With the advent of novel devices and the progression of technology, these devices exhibit a multitude of interrelated factors and demonstrate a nonlinear correlation. Triangular Gate (TG) FinFETs technology has emerged as a possible alternative for addressing the limitations of traditional planar transistors in present integrated circuits (ICs). This paper presents an effective data-driven Multiobjective Optimization (MOO) with evolutionary computation (EC) techniques. By using these techniques, TG FinFETs enables the automated identification of optimal design that balances the transistor speed, power, and variability. To assist in the design of TG FinFETs, this study integrated two popular MOO techniques such as PAL and NSGA-III. These algorithms effectively handle the complicated trade-offs between diverse objectives and allow for efficient and effective TG FinFETs design optimization.</p>\u0000 </div>","PeriodicalId":50300,"journal":{"name":"International Journal of Numerical Modelling-Electronic Networks Devices and Fields","volume":"38 2","pages":""},"PeriodicalIF":1.6,"publicationDate":"2025-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143689018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}