IEEE Journal on Emerging and Selected Topics in Circuits and Systems最新文献

Guest Editorial 2.5D/3D Chiplet Circuits and Systems, EDA, Advanced Packaging, and Test—Part I 客座编辑2.5D/3D芯片电路和系统，EDA，先进封装和测试

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2025-09-16 DOI: 10.1109/JETCAS.2025.3600772

Qinfen Hao;Kuan-Neng Chen;Sandeep Kumar Goel;Hai Li;Erik Jan Marinissen

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IEEE Journal on Emerging and Selected Topics in Circuits and Systems Information for Authors IEEE关于电路和系统信息中新兴和选定主题的作者期刊

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2025-09-15 DOI: 10.1109/JETCAS.2025.3603800

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IEEE Journal on Emerging and Selected Topics in Circuits and Systems IEEE电路与系统中新兴和选定主题杂志

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2025-09-15 DOI: 10.1109/JETCAS.2025.3603804

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IEEE Journal on Emerging and Selected Topics in Circuits and Systems Publication Information IEEE关于电路和系统中新兴和选定主题的期刊出版信息

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2025-09-15 DOI: 10.1109/JETCAS.2025.3603802

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Optimizing Thermal Performance in 2.5D Systems Using Embedded Isolators 使用嵌入式隔离器优化2.5D系统的热性能

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2025-08-05 DOI: 10.1109/JETCAS.2025.3595909

George Karfakis;Myriam Bouzidi;Yunhyeok Im;Alexander Graening;Suresh K. Sitaraman;Puneet Gupta

{"title":"Optimizing Thermal Performance in 2.5D Systems Using Embedded Isolators","authors":"George Karfakis;Myriam Bouzidi;Yunhyeok Im;Alexander Graening;Suresh K. Sitaraman;Puneet Gupta","doi":"10.1109/JETCAS.2025.3595909","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3595909","url":null,"abstract":"This paper investigates thermal management in tightly integrated heterogeneous chiplet systems, focusing on a novel approach using embedded thermal isolators. In many 2.5D systems, such as modern enterprise GPUs, thermally sensitive chiplets like High Bandwidth Memory (HBM) are thermally coupled to high-power compute chiplets, leading to performance degradation. We propose and evaluate the use of thermal isolators embedded within the heat spreader to effectively thermally decouple chiplets. Our thermal simulations of a water-cooled 2.5D integrated GPU system indicate that conventional approaches like thermally-aware floorplanning are less effective due to the dominant heat transfer through the heat spreader. In contrast, our proposed thermal isolators can significantly increase thermal isolation between chiplets (by up to 61%), or even reduce overall average peak chip temperature (by up to 22.5%). We develop a closed-loop workflow incorporating thermal results to quantify performance impacts of thermal-induced throttling, finding that in an example GPU+HBM system, the isolator approach can yield performance gains of up to 37% for memory-bound workloads. These findings open up new avenues for thermal management and thermal-system co-optimization in 2.5D heterogeneous integrated systems, potentially enabling more efficient and higher-performing chiplet-based architectures.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 3","pages":"458-468"},"PeriodicalIF":3.8,"publicationDate":"2025-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145061945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

SAFET-HI: Secure Authentication-Based Framework for Encrypted Testing in Heterogeneous Integration 基于安全认证的异构集成加密测试框架

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2025-08-01 DOI: 10.1109/JETCAS.2025.3594675

Galib Ibne Haidar;Jingbo Zhou;Md Sami Ul Islam Sami;Mark M. Tehranipoor;Farimah Farahmandi

{"title":"SAFET-HI: Secure Authentication-Based Framework for Encrypted Testing in Heterogeneous Integration","authors":"Galib Ibne Haidar;Jingbo Zhou;Md Sami Ul Islam Sami;Mark M. Tehranipoor;Farimah Farahmandi","doi":"10.1109/JETCAS.2025.3594675","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3594675","url":null,"abstract":"System-in-Packages (SiPs) are gaining traction due to their enhanced performance, high yield rates, and accelerated time-to-market. However, integrating chiplets from untrusted sources introduces security risks during post-integration testing. Malicious chiplets within the SiP can intercept, modify, or block sensitive test data intended for specific chiplets. This article presents SAFET-HI, a framework designed to ensure a secure testing environment for SiPs. Within this framework, sensitive test data are accessible only to authenticated chiplets. To counter sniffing and spoofing attacks, SAFET-HI encrypts sensitive test patterns while maintaining minimal timing overhead. During post-integration testing, another major threat arises from outsourcing test patterns to untrusted testing facilities, increasing the risk of overproduction and counterfeiting. To address this, SAFET-HI incorporates a functional locking mechanism that prevents unauthorized production and distribution of defective SiPs. Additionally, scan encryption blocks are implemented to stop untrusted test facilities from generating a golden response database. To further enhance security, a watermark bitstream is embedded within the SiP to prevent remarking attacks by untrusted distributors. Simulation results show that SAFET-HI incurs area and timing overheads of only 1.42-4.27% and 13.7%, respectively, demonstrating its effectiveness in securing the SiP testing process.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 3","pages":"478-492"},"PeriodicalIF":3.8,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145061894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Miniaturized and Cost-Effective Programmable 2.5D/3.5D Platforms Enabled by Scalable Embedded Active Bridge Chipset 可扩展嵌入式有源桥芯片组支持小型化和高性价比的可编程2.5D/3.5D平台

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2025-07-30 DOI: 10.1109/JETCAS.2025.3594169

Wei Lu;Jie Zhang;Yi-Hui Wei;Hsu-Ming Hsiao;Sih-Han Li;Chao-Kai Hsu;Chih-Cheng Hsiao;Feng-Hsiang Lo;Shyh-Shyuan Sheu;Chin-Hung Wang;Ching-Iang Li;Yung-Sheng Chang;Ming-Ji Dai;Wei-Chung Lo;Shih-Chieh Chang;Hung-Ming Chen;Kuan-Neng Chen;Po-Tsang Huang

{"title":"Miniaturized and Cost-Effective Programmable 2.5D/3.5D Platforms Enabled by Scalable Embedded Active Bridge Chipset","authors":"Wei Lu;Jie Zhang;Yi-Hui Wei;Hsu-Ming Hsiao;Sih-Han Li;Chao-Kai Hsu;Chih-Cheng Hsiao;Feng-Hsiang Lo;Shyh-Shyuan Sheu;Chin-Hung Wang;Ching-Iang Li;Yung-Sheng Chang;Ming-Ji Dai;Wei-Chung Lo;Shih-Chieh Chang;Hung-Ming Chen;Kuan-Neng Chen;Po-Tsang Huang","doi":"10.1109/JETCAS.2025.3594169","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3594169","url":null,"abstract":"This paper presents the Embedded Multi-die Active Bridge (EMAB) chip, a programmable bridge for cost-effective 2.5D/3.5D packaging technologies. The EMAB chip features a reconfigurable switch array to establish flexible I/O links for connecting multiple chiplets, forming an EMAB chipset based on user needs. It integrates low-dropout regulators (LDOs) for in-package voltage regulation and supports various transmission interfaces, including checkerboard I/Os (50 Mbps–1 Gbps) and MUX I/Os (up to 8 Gbps). Moreover, multiple EMAB chips can be interconnected in a daisy-chain configuration, enabling easy expansion of the EMAB chipset. Additionally, the EMAB chip eliminates TSVs in silicon interposer-based 2.5D packaging technologies and reduces redistribution layer (RDL) complexity through flexible I/O links established within the EMAB chip. Furthermore, EMAB chip can be pre-manufactured as a precast supporting layer (known good die, KGD), which shortens the product development cycle and enhance integration yield. Overall, the EMAB chip offers a miniaturized, low-cost, fast time-to-market and scalable solution for advanced 2.5D/3.5D packaging.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 3","pages":"379-391"},"PeriodicalIF":3.8,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145061909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Enhancing DFT Security in Chiplet-Based Systems With Encryption and Integrity Checking 用加密和完整性检查增强基于芯片系统的DFT安全性

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2025-07-28 DOI: 10.1109/JETCAS.2025.3592984

Juan Suzano;Anthony Philippe;Fady Abouzeid;Giorgio Di Natale;Philippe Roche

{"title":"Enhancing DFT Security in Chiplet-Based Systems With Encryption and Integrity Checking","authors":"Juan Suzano;Anthony Philippe;Fady Abouzeid;Giorgio Di Natale;Philippe Roche","doi":"10.1109/JETCAS.2025.3592984","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3592984","url":null,"abstract":"Chiplet-based chips are the natural evolution of traditional 2D SoCs. In the future, off-the-shelf chiplets are expected to represent an important component of the semiconductor industry. The IEEE Std 1838(TM)-2019 design-for-testability (DFT) standard enable testing of stacked chiplets from multiple vendors. However, the shared DFT network threatens the confidentiality and integrity of test data and other sensitive information. This paper addresses the security concerns associated with DFT infrastructures in chiplet-based systems. We discuss the necessity of securing DFT infrastructures to prevent unauthorized access and malicious activities. Furthermore, we propose a hardware countermeasure that combines encryption and encoding to secure communication over the DFT network. Results show that the DFT can be protected from misbehavior from malicious chiplets on the stack, scan-based attacks, and brute force attacks with minimal overhead in terms of area and test time. The proposed solution causes less than 1% area overhead on designs composed of more than 5 million gates and less than 1% test time overhead for typical DFT implementations.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 3","pages":"493-505"},"PeriodicalIF":3.8,"publicationDate":"2025-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145061903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Through Silicon Via (TSV) Architecture of the Bumpless Build Cube (BBCube) for Stacked Memory Devices 一种用于堆叠存储器器件的无碰撞构建立方体（BBCube）的TSV架构

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2025-07-22 DOI: 10.1109/JETCAS.2025.3591627

Shinji Sugatani;Hiroyuki Ryoson;Norio Chujo;Masao Taguchi;Koji Sakui;Takayuki Ohba

{"title":"A Through Silicon Via (TSV) Architecture of the Bumpless Build Cube (BBCube) for Stacked Memory Devices","authors":"Shinji Sugatani;Hiroyuki Ryoson;Norio Chujo;Masao Taguchi;Koji Sakui;Takayuki Ohba","doi":"10.1109/JETCAS.2025.3591627","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3591627","url":null,"abstract":"This paper describes the architecture of the wafer-on-wafer (WOW) via-last through silicon via (TSV), named Bumpless Build Cube-TSV (BBCube-TSV). At first, the three types of TSVs, <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>-bump technology, hybrid bonding technology, and BBCube-TSV are overviewed, addressing the detailed structures and the opportunities of applying for 3D-memories. Then, the process steps of the BBCube-TSV are summarized to figure out the key process steps. Three types of applications are reviewed to illustrate and discuss the potentiality of the BBCube-TSV to enhance 3D-memories, power delivery wiring in processor on stacked memory devices, and advantage in defect management with sophisticated ideas on stacked memories. The simplicity of the structure and the occupation of copper in the TSV structure are found to provide the advantages. The role of the TSV as a vertical interconnect in the hierarchy of multilayer wiring is discussed.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 3","pages":"368-378"},"PeriodicalIF":3.8,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11088080","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145059835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Bumpless Build Cube (BBCube) 3D: Heterogeneous 3D Integration Using WOW and COW 无碰撞构建立方体（BBCube） 3D：使用WOW和COW的异构3D集成

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2025-07-22 DOI: 10.1109/JETCAS.2025.3591677

Norio Chujo;Hiroyuki Ryoson;Koji Sakui;Shinji Sugatani;Masao Taguchi;Takayuki Ohba

{"title":"Bumpless Build Cube (BBCube) 3D: Heterogeneous 3D Integration Using WOW and COW","authors":"Norio Chujo;Hiroyuki Ryoson;Koji Sakui;Shinji Sugatani;Masao Taguchi;Takayuki Ohba","doi":"10.1109/JETCAS.2025.3591677","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3591677","url":null,"abstract":"We propose a novel technology called Bumpless Build Cube (BBCubeTM) 3D for AI and high-performance computing (HPC) applications that require high bandwidth and power efficiency. BBCube 3D is constructed through heterogeneous 3D integration, in which xPU (e.g., CPU, GPU, TPU) chiplets and DRAM dies are stacked using a combination of bumpless wafer-on-wafer (WoW) and chip-on-wafer (CoW) processes. The bumpless stacking process adopts a method similar to multilevel metallization in the back-end-of-line (BEOL), enabling BBCube to provide reliable and high-density interconnects between dies. Moreover, BBCube features low-capacitance and low-impedance through-silicon vias (TSVs) due to the use of thin silicon and slim TSV structures. To further enhance performance, a highly parallel DRAM architecture leveraging the bumpless WoW process is introduced. The high-density TSVs enable lower data transmission speeds without compromising bandwidth. Additionally, the adoption of four-phase shielded I/Os (FPS-I/O) allows for a reduction in power supply voltage. BBCube 3D has the potential to achieve a bandwidth 30 times higher than DDR5 and four times higher than HBM2E, while achieving bit access energy consumption reduced to one-twentieth that of DDR5 and one-fifth that of HBM2E. The low-impedance TSVs in BBCube ensure robust power integrity for the xPU stacked on top of the layered DRAM. Furthermore, integrating an xPU on top of the Cube enables efficient cooling of high-power xPUs. BBCube can accommodate an xPU with a power density exceeding 50 W/cm<sup>2</sup> — comparable to the latest GPUs — while maintaining the DRAM temperature below 95°C.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 3","pages":"404-414"},"PeriodicalIF":3.8,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145061955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0