IEEE Journal on Emerging and Selected Topics in Circuits and Systems最新文献

A Twin-FeFET MLC CIM With Enhanced Voltage and Process Variation Tolerance for Edge Intelligence MAC and AP 用于边缘智能MAC和AP的具有增强电压和工艺变化容忍度的双fet MLC CIM

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-09-01 Epub Date: 2026-03-22 DOI: 10.1109/JETCAS.2026.3696148

Zhihao Li;Shuo Yang;Lubin Xiang;Xiaobo Gong;Xiaohang Chen;Wei Hu;Zhiting Lin;Xiulong Wu;Chunyu Peng

{"title":"A Twin-FeFET MLC CIM With Enhanced Voltage and Process Variation Tolerance for Edge Intelligence MAC and AP","authors":"Zhihao Li;Shuo Yang;Lubin Xiang;Xiaobo Gong;Xiaohang Chen;Wei Hu;Zhiting Lin;Xiulong Wu;Chunyu Peng","doi":"10.1109/JETCAS.2026.3696148","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3696148","url":null,"abstract":"This paper introduces a voltage and process variation-tolerant non-volatile computing-in-memory (CIM) architecture based on the co-design of neural networks and circuit implementations. By exploiting the adjustable threshold voltage (<inline-formula> <tex-math>$V_{TH}$ </tex-math></inline-formula>) of ferroelectric field-effect transistors (FeFETs), the proposed architecture features an active square-law compensation mechanism within a 2-FeFET-1-Transistor-1-Capacitor (2F-1T-1C) single cell (S-Cell) to perform highly linear multiply-accumulate (MAC) computations. To further enable high-precision operations and global average pooling (AP), we propose a twin-cell (T-Cell) extension (FeMAPIM). The T-Cell leverages an asymmetric capacitive ratio (4:1) that not only drastically reduces the average per-cell capacitor area overhead but also acts as a spatial filter for variations. The architecture is comprehensively evaluated across cell and array levels. System-level assessments on VGG-GAP, ResNet-20, and MobileNetV2 using CIFAR datasets confirm that the proposed macro tightly suppresses hardware-induced accuracy degradation, delivering highly robust inference for edge intelligence.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 3","pages":"648-660"},"PeriodicalIF":3.8,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149133402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Analog Integrated, Power-Efficient, Current-Mode Type-2 Fuzzy Inference System for Biomedical Applications 生物医学应用的模拟集成、节能、电流模式2型模糊推理系统

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-09-01 Epub Date: 2026-07-30 DOI: 10.1109/JETCAS.2026.3718829

Vassilis Alimisis;Andreas Papathanasiou;Vasileios Moustakas;Anna Mylona;Daniela Papa;Alak Majumder;Paul P. Sotiriadis

{"title":"An Analog Integrated, Power-Efficient, Current-Mode Type-2 Fuzzy Inference System for Biomedical Applications","authors":"Vassilis Alimisis;Andreas Papathanasiou;Vasileios Moustakas;Anna Mylona;Daniela Papa;Alak Majumder;Paul P. Sotiriadis","doi":"10.1109/JETCAS.2026.3718829","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3718829","url":null,"abstract":"This work presents a low-power, current-mode, analog Type-2 Fuzzy Inference System (FIS) architecture implemented in a TSMC 65-nm CMOS process and evaluated on two biomedical classification tasks. The architecture comprises analog CMOS building blocks that implement membership computation, rule evaluation, and defuzzification, all operating in the subthreshold region. All blocks are parametrically tunable, enabling full system-level optimization. The supply voltage is set to ±0.3 V, resulting in ultra-low-power operation while maintaining an acceptable noise power spectral density. Monte Carlo post-layout simulation results demonstrate a worst-case classification accuracy of 88.7% and strong robustness against device mismatch as well as Process–Voltage–Temperature (PVT) variations. With an average power consumption of <inline-formula> <tex-math>$1.076~mu $ </tex-math></inline-formula>W and a worst-case power consumption of <inline-formula> <tex-math>$1.247~mu $ </tex-math></inline-formula>W across PVT corners, the system is well suited for deployment in energy-limited edge-AI platforms for continuous biomedical monitoring and diagnostic applications.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 3","pages":"789-805"},"PeriodicalIF":3.8,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148985585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Drift-Resilient PCM-Based Analog In-Memory Computing for Tactile Sensing in Human--Robot Interaction: Efficient Feature Extraction 基于漂移弹性pcm的人-机器人交互触觉模拟内存计算：高效特征提取

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-09-01 Epub Date: 2026-06-08 DOI: 10.1109/JETCAS.2026.3701542

Adnan Haidar;Pawel Kostka;Vasileios Ntinas;Ronald Tetzlaff

{"title":"Drift-Resilient PCM-Based Analog In-Memory Computing for Tactile Sensing in Human--Robot Interaction: Efficient Feature Extraction","authors":"Adnan Haidar;Pawel Kostka;Vasileios Ntinas;Ronald Tetzlaff","doi":"10.1109/JETCAS.2026.3701542","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3701542","url":null,"abstract":"Analog in-memory computing (AIMC) with phase-change memory (PCM) offers substantial energy efficiency gains for edge inference by executing matrix–vector multiplications (MVMs) directly in memory, making it well suited to real-time tactile perception in robotics. A fundamental reliability challenge of PCM is conductance drift, a time-dependent stochastic reduction caused by structural relaxation that degrades inference accuracy over time. This paper presents a drift-resilient architecture that couples electrical time-domain reflectometry (ETDR) tactile sensing with PCM-based AIMC for human-robot interaction (HRI). In ETDR, touch-induced deformations create localized impedance discontinuities along an embedded transmission line, producing reflected RF signals that encode force magnitude and contact location in high-dimensional reflectograms. Based on this sensing modality, we evaluate a heterogeneous processing pipeline with three feature-extraction strategies under identical training and drift conditions: parameter-free Robust Segment Statistics (RSS), digitally executed PCA (PCA-D), and PCA mapped to analog crossbars (PCA-A). RSS matches PCA-D within 0.33 percentage points (pp) in digital accuracy, whereas PCA-A exhibits roughly twice the one-year drift degradation of PCA-D, indicating the penalty of mapping learned preprocessing to analog crossbars under the adopted drift model. Drift-aware regularization (DAR) improves RSS one-year force-classification accuracy from 86.87% to 88.03%, recovering 22.4% of the drift-induced loss, while PCA-D achieves a one-year localization error of 29.4 mm. These results suggest that keeping learned preprocessing parameters in the digital domain while applying physics-informed training to the analog classifier is a promising design principle for drift-resilient AIMC tactile inference in resource-constrained HRI systems.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 3","pages":"684-698"},"PeriodicalIF":3.8,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148985584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Variability Analysis of Memristor Crossbar Arrays: A Probabilistic Machine Learning Assisted Metaheuristic Framework 忆阻器横栅阵列的可变性分析：一个概率机器学习辅助的元启发式框架

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-09-01 Epub Date: 2026-08-05 DOI: 10.1109/JETCAS.2026.3720989

Joel Thomas;Aswani Radhakrishnan;Jai Narayan Tripathi;Alex James

{"title":"Variability Analysis of Memristor Crossbar Arrays: A Probabilistic Machine Learning Assisted Metaheuristic Framework","authors":"Joel Thomas;Aswani Radhakrishnan;Jai Narayan Tripathi;Alex James","doi":"10.1109/JETCAS.2026.3720989","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3720989","url":null,"abstract":"Memristor crossbar arrays have emerged as a promising technology for future memory and computing systems due to their high density, low power consumption, and non-volatile behavior. As the demand for more powerful and energy-efficient electronic devices continues to grow, large-scale memristor crossbar arrays have gained significant attention in both academic research and industrial applications. However, the practical deployment of these arrays faces various challenges related to device variability, which can significantly impact their performance and reliability. This research proposes a novel framework for estimating variability in large memristor crossbar arrays using surrogate-assisted metaheuristic approach. The use of Gaussian Process Regressor (GPR) as the surrogate model is explored in this work. The study aims to understand the effect of variability, quantify its impact on array performance, and demonstrate the efficacy of the proposed method for fast estimation of variability. Each individual cell in the crossbar array is made up of one transistor one memristor (1T1M) unit. The variability obtained from the surrogate-assisted method is compared with conventional metaheuristic approaches, polynomial chaos expansion (PCE) and Monte Carlo (MC) simulations. The surrogate model is further validated at the distribution level against MC. Here, when training database reaches the order of the parameter count, the GPR reproduces the MC statistics (i.e. the probability density, standard deviation, skewness) with a point-wise correlation of <inline-formula> <tex-math>$r=0.997$ </tex-math></inline-formula> on unseen samples.The results are cross-verified on an independent, SPICE testbench (ngspice), and we observe that the two testbenches agree with a correlation of <inline-formula> <tex-math>$r=1.000$ </tex-math></inline-formula> on identical parameter sets, with the the Monte Carlo statistics match within 1%.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 3","pages":"826-838"},"PeriodicalIF":3.8,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148985726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Investigation of Oscillatory Neural Networks With Verilog-A Models of VO2 Relaxation Oscillators and Analog RRAM Coupling Elements 用Verilog-A模型研究VO2松弛振荡器和模拟RRAM耦合元件的振荡神经网络

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-09-01 Epub Date: 2026-06-19 DOI: 10.1109/JETCAS.2026.3705420

Renate Debets;Matteo Galetta;Tommaso Negrini;Jelle Verest;Simanta Lahkar;Donato Francesco Falcone;Siegfried Karg;Valeria Bragaglia;Aida Todri-Sanial

{"title":"Investigation of Oscillatory Neural Networks With Verilog-A Models of VO2 Relaxation Oscillators and Analog RRAM Coupling Elements","authors":"Renate Debets;Matteo Galetta;Tommaso Negrini;Jelle Verest;Simanta Lahkar;Donato Francesco Falcone;Siegfried Karg;Valeria Bragaglia;Aida Todri-Sanial","doi":"10.1109/JETCAS.2026.3705420","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3705420","url":null,"abstract":"Oscillatory Neural Networks (ONNs) exploit the rich phase dynamics of coupled oscillators to perform parallel, in-memory, and inherently analog computation. By encoding information in relative phase differences, ONNs can efficiently solve complex optimization and pattern-recognition tasks while mitigating data-movement bottlenecks inherent to conventional von Neumann architectures. To date, most ONNs have relied on CMOS-based ring oscillators, whose scalability is limited by field-effect transistor constraints and complex coupling circuitry. This work explores alternative device technologies compatible with Back-End-of-Line (BEOL) integration, combining Vanadium Dioxide (VO2) relaxation oscillators with analog Resistive Random Access Memory (RRAM) coupling elements. Compact Verilog-A models for both VO2 and RRAM devices are developed and validated against experimental data, enabling circuit-level exploration of coupled dynamics, biasing conditions, and device compatibility. These models and simulation tools establish a foundation for co-designing scalable VO2–RRAM ONN architectures, supporting the development of energy-efficient, BEOL-integrated in-memory computing systems.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 3","pages":"816-825"},"PeriodicalIF":3.8,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148985859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Guest Editorial Advances in Analog and Mixed-Signal Computing: Architectures, Theory, and Applications---Part I: Emerging Devices and Memory-Centric Hardware for Analog Learning and Inference 模拟和混合信号计算的进展：架构、理论和应用——第一部分：用于模拟学习和推理的新兴设备和以内存为中心的硬件

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-09-01 Epub Date: 2026-09-24 DOI: 10.1109/JETCAS.2026.3724813

Paul P. Sotiriadis;Gert Cauwenberghs;Yiran Chen;Abu Sebastian

引用次数: 0

End-to-End Analog Edge AI Architecture for Scalable Energy-Efficient On-Chip Learning 端到端模拟边缘AI架构，用于可扩展的节能片上学习

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-09-01 Epub Date: 2026-06-10 DOI: 10.1109/JETCAS.2026.3702592

Mohamed Watfa;Alberto Garcia-Ortiz;Gilles Sassatelli

{"title":"End-to-End Analog Edge AI Architecture for Scalable Energy-Efficient On-Chip Learning","authors":"Mohamed Watfa;Alberto Garcia-Ortiz;Gilles Sassatelli","doi":"10.1109/JETCAS.2026.3702592","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3702592","url":null,"abstract":"Equilibrium Propagation (EP) offers an attractive learning framework for analog and mixed-signal neural hardware by expressing learning as a perturbation of physical equilibrium dynamics. However, practical deployment has been limited by sensitivity to voltage variations, device non-idealities, and learning rules that are poorly matched to circuit constraints. As a result, existing EP hardware demonstrations remain difficult to scale beyond small or idealized settings. This work presents an end-to-end mixed-signal learning architecture based on EP and a hardware-driven analysis of update rules, batching, and gradient quantization under realistic analog and memristive conditions. A systematic evaluation shows that several commonly used EP formulations fail to provide stable learning when circuit effects are considered. To address this, a quantized reformulation derived from the EP adjoint update is introduced and implemented using switched-capacitor charge-domain accumulation, enabling intrinsic batching and low-precision operation. SPICE-level simulations on Iris and MNIST demonstrate stable convergence with 2–4 bit gradients and consistent performance gains over prior hardware-oriented EP implementations, indicating that scalable on-chip EP training is achievable under realistic hardware constraints.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 3","pages":"775-788"},"PeriodicalIF":3.8,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148985797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

On the Viability of End-to-End Neural Networks in the Analog Domain 端到端神经网络在模拟领域的可行性

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-09-01 Epub Date: 2026-06-12 DOI: 10.1109/JETCAS.2026.3703087

Afolabi Ige;Praveen Raj Ayyappan;Jennifer Hasler

引用次数: 0

Hardware-Aware Model Design and Training of Silicon-Based Analog Neural Networks 基于硅的模拟神经网络的硬件感知模型设计与训练

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-09-01 Epub Date: 2026-06-19 DOI: 10.1109/JETCAS.2026.3705439

Giulio Filippeschi;Mirko Brazzini;Cristhopher Mosquera;Marco Lanuzza;Alessandro Catania;Sebastiano Strangio;Giuseppe Iannaccone

{"title":"Hardware-Aware Model Design and Training of Silicon-Based Analog Neural Networks","authors":"Giulio Filippeschi;Mirko Brazzini;Cristhopher Mosquera;Marco Lanuzza;Alessandro Catania;Sebastiano Strangio;Giuseppe Iannaccone","doi":"10.1109/JETCAS.2026.3705439","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3705439","url":null,"abstract":"Silicon-based analog neural networks physically embody the ideal neural network model in an approximate way. We show that by retraining the neural network using a physics-informed hardware-aware model one can fully recover the inference accuracy of the ideal network model even in the presence of significant non-idealities. This is way more promising for scalability and integration density than the default option of improving the fidelity of the analog neural network at the cost of significant energy, area, and design overhead, through extensive calibration and conservative analog design. We first present a physics-informed hardware-aware model for a time-domain vector-matrix multiplier implemented with single-transistor floating-gate memory cells that explicitly accounts for two dominant non-idealities of the physical implementation—capacitive crosstalk and bit-line voltage drop— and integrates seamlessly with modern deep-learning workflows. The model discretizes each operation into adaptive time slots, processes activation patterns in parallel, and accumulates their contributions to predict effective multiplier outputs. Using measurements from a 16<inline-formula> <tex-math>$times$ </tex-math></inline-formula>16 silicon array demonstrator, we show that crosstalk is layout-dependent and often dominant and we introduce an improved weight-extraction procedure that doubles signal-to-error ratio versus an ideal vector-matrix multiplier model. Finally, we show that by training silicon-based analog neural networks using a hardware-aware model in the forward pass we can recover the accuracy of the ideal software networks across six architectures on datasets of increasing complexity, establishing a complete design-to-deployment workflow for timedomain analog neuromorphic chips.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 3","pages":"752-762"},"PeriodicalIF":3.8,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11571789","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148985795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Improved Spin Transport in Co2FeAl Magnetic Tunnel Junctions With Symmetric Hybrid MgO/WSe2/MgO Barriers 对称MgO/WSe2/MgO杂化势垒改善Co2FeAl磁隧道结的自旋输运

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-09-01 Epub Date: 2026-08-06 DOI: 10.1109/JETCAS.2026.3721362

Shagufta Parveen Asif Akhtar;Santashraya Prasad;Md. Waseem Akram;Aminul Islam

{"title":"Improved Spin Transport in Co2FeAl Magnetic Tunnel Junctions With Symmetric Hybrid MgO/WSe2/MgO Barriers","authors":"Shagufta Parveen Asif Akhtar;Santashraya Prasad;Md. Waseem Akram;Aminul Islam","doi":"10.1109/JETCAS.2026.3721362","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3721362","url":null,"abstract":"This work reports a first-principles study of a hybrid-barrier magnetic tunnel junction (MTJ) with the stack Co2FeAl/MgO/WSe2/MgO/Co2FeAl, modeled using density-functional theory (DFT) combined with a non-equilibrium Green’s-function (NEGF) transport framework in QuantumATK. The symmetric device yields a tunneling magnetoresistance (TMR) of about 170% at 300 K, indicating strong spin-dependent tunneling suitable for room-temperature spintronic operation. To assess the impact of structural asymmetry, two modified hybrid-barrier junctions were examined in which the left-side (skip-L) or right-side (skip-R) MgO sublayer was removed, giving WSe2/MgO and MgO/WSe2 hybrid-barriers. In these asymmetric configurations, the TMR drops to <inline-formula> <tex-math>$sim ~19$ </tex-math></inline-formula>% at 300 K, demonstrating that the loss of symmetric MgO confinement substantially weakens <inline-formula> <tex-math>$Delta _{1}$ </tex-math></inline-formula>-like coherent tunneling and spin-selective transmission. Overall, the results show that a symmetric MgO/WSe2/MgO barrier can effectively merge the coherent tunneling characteristics of MgO with the spin-filtering behavior of WSe2, leading to a thermally robust, high-TMR Co2FeAl-based MTJ that is well suited for spintronic memory applications.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 3","pages":"806-815"},"PeriodicalIF":3.8,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148985827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0