基于安全认证的异构集成加密测试框架

IF 3.8 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
Galib Ibne Haidar;Jingbo Zhou;Md Sami Ul Islam Sami;Mark M. Tehranipoor;Farimah Farahmandi
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引用次数: 0

摘要

系统级封装(sip)由于其增强的性能、高产出率和加速的上市时间而受到越来越多的关注。但是,集成来自不可信来源的小程序会在集成后测试期间引入安全风险。SiP内的恶意小芯片可以拦截、修改或阻断特定小芯片的敏感测试数据。本文介绍了safe - hi,这是一个旨在确保sip安全测试环境的框架。在这个框架中,敏感的测试数据只有经过身份验证的小芯片才能访问。为了对抗嗅探和欺骗攻击,SAFET-HI对敏感的测试模式进行加密,同时保持最小的定时开销。在集成后测试期间,另一个主要威胁来自于将测试模式外包给不可信的测试机构,增加了生产过剩和伪造的风险。为了解决这个问题,SAFET-HI采用了功能性锁定机制,防止未经授权生产和分发有缺陷的sip。此外,还实现了扫描加密块,以阻止不受信任的测试设施生成黄金响应数据库。为了进一步提高安全性,在SiP协议中嵌入水印比特流,以防止不可信分发者的备注攻击。仿真结果表明,SAFET-HI的面积开销和时间开销分别仅为1.42-4.27%和13.7%,证明了其在SiP测试过程中的有效性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
SAFET-HI: Secure Authentication-Based Framework for Encrypted Testing in Heterogeneous Integration
System-in-Packages (SiPs) are gaining traction due to their enhanced performance, high yield rates, and accelerated time-to-market. However, integrating chiplets from untrusted sources introduces security risks during post-integration testing. Malicious chiplets within the SiP can intercept, modify, or block sensitive test data intended for specific chiplets. This article presents SAFET-HI, a framework designed to ensure a secure testing environment for SiPs. Within this framework, sensitive test data are accessible only to authenticated chiplets. To counter sniffing and spoofing attacks, SAFET-HI encrypts sensitive test patterns while maintaining minimal timing overhead. During post-integration testing, another major threat arises from outsourcing test patterns to untrusted testing facilities, increasing the risk of overproduction and counterfeiting. To address this, SAFET-HI incorporates a functional locking mechanism that prevents unauthorized production and distribution of defective SiPs. Additionally, scan encryption blocks are implemented to stop untrusted test facilities from generating a golden response database. To further enhance security, a watermark bitstream is embedded within the SiP to prevent remarking attacks by untrusted distributors. Simulation results show that SAFET-HI incurs area and timing overheads of only 1.42-4.27% and 13.7%, respectively, demonstrating its effectiveness in securing the SiP testing process.
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来源期刊
CiteScore
8.50
自引率
2.20%
发文量
86
期刊介绍: The IEEE Journal on Emerging and Selected Topics in Circuits and Systems is published quarterly and solicits, with particular emphasis on emerging areas, special issues on topics that cover the entire scope of the IEEE Circuits and Systems (CAS) Society, namely the theory, analysis, design, tools, and implementation of circuits and systems, spanning their theoretical foundations, applications, and architectures for signal and information processing.
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