IEEE Journal on Emerging and Selected Topics in Circuits and Systems最新文献_第2页

Large-Margin Dynamic Memory Refresh for Persistent In-Memory Computing and Learning 用于持久内存计算和学习的大余量动态内存刷新

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-09-01 Epub Date: 2026-06-17 DOI: 10.1109/JETCAS.2026.3704740

Samira Sebt;Johannes Leugering;Georgios Gennis;Gert Cauwenberghs

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IEEE Journal on Emerging and Selected Topics IEEE新兴和选定主题杂志

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-09-01 Epub Date: 2026-09-18 DOI: 10.1109/JETCAS.2026.3726574

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Capacitive Crossbar Array as a Non-Iterative Least-Squares Solver in Real-Time Broadband Beamforming 电容横杆阵列在实时宽带波束形成中的非迭代最小二乘求解方法

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-09-01 Epub Date: 2026-06-19 DOI: 10.1109/JETCAS.2026.3705418

Madhav Vadlamani;Nakul Singh;Coleman DeLude;Justin Romberg;Shimeng Yu

{"title":"Capacitive Crossbar Array as a Non-Iterative Least-Squares Solver in Real-Time Broadband Beamforming","authors":"Madhav Vadlamani;Nakul Singh;Coleman DeLude;Justin Romberg;Shimeng Yu","doi":"10.1109/JETCAS.2026.3705418","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3705418","url":null,"abstract":"This work demonstrates a compute-in-memory (CIM) capacitive crossbar array that solves the core least-squares problems of broadband Slepian beamforming non-iteratively for batch processing and in real-time for streaming data, eliminating the need for iterative algorithms, auxiliary crossbars, or complex digital peripherals. Our analog CIM architecture directly computes the solution to <inline-formula> <tex-math>$boldsymbol {A}boldsymbol {alpha } =boldsymbol {b}$ </tex-math></inline-formula> through charge-domain matrix inversion. The design exploits non-volatile ferroelectric capacitors (nvCAPs) to store matrix weights, enabling in-situ computation with zero static power and <inline-formula> <tex-math>$1000times $ </tex-math></inline-formula> higher energy efficiency than the resistive CIM counterpart. SPICE simulations show 0.1% normalized mean squared error (MSE) and < 0.5 dB beamforming gain loss. By circumventing iterative algorithms and machine learning (ML)’s data dependency, this work provides a physics-based, hardware-efficient path for real-time broadband beamforming.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 3","pages":"673-683"},"PeriodicalIF":3.8,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148985674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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IEEE Journal on Emerging and Selected Topics in Circuits and Systems IEEE电路与系统中新兴和选定主题杂志

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-09-01 Epub Date: 2026-09-18 DOI: 10.1109/JETCAS.2026.3726568

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Cross-Domain Acceleration of Open Modification Search: From Commodity Platforms to Emerging Memory and Storage Devices 开放修改搜索的跨领域加速：从商品平台到新兴存储器和存储设备

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-09-01 Epub Date: 2026-06-08 DOI: 10.1109/JETCAS.2026.3701551

Sumukh Pinge;Chang Eun Song;Po-Kai Hsu;Zheyu Li;Ashkan Moradifirouzabadi;Yanru Chen;Xiangjin Wu;Wei-Chen Chen;Eric Pop;Shimeng Yu;H.-S. Philip Wong;Tajana Rosing;Mingu Kang

{"title":"Cross-Domain Acceleration of Open Modification Search: From Commodity Platforms to Emerging Memory and Storage Devices","authors":"Sumukh Pinge;Chang Eun Song;Po-Kai Hsu;Zheyu Li;Ashkan Moradifirouzabadi;Yanru Chen;Xiangjin Wu;Wei-Chen Chen;Eric Pop;Shimeng Yu;H.-S. Philip Wong;Tajana Rosing;Mingu Kang","doi":"10.1109/JETCAS.2026.3701551","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3701551","url":null,"abstract":"Open modification search (OMS) in mass spectrometry (MS) is a data-intensive workload whose performance is dominantly limited by reference data movement rather than computation. Prior OMS accelerators have largely been evaluated in isolation, making it difficult to understand system-level trade-offs across platforms. This paper presents the first workload-driven, cross-platform survey of accelerators for MS search by studying not only commodity platforms, but also emerging memory- and storage-centric architectures, including GPUs, near-storage FPGAs, DRAM near-memory processing, ReRAM/PCM in-memory processing, and 3D NAND/FeNAND in-storage processing, under consistent algorithmic and accuracy assumptions. Leveraging a binary hyperdimensional computing (HDC)–based OMS formulation that reduces similarity evaluation to lightweight bitwise primitives and tolerates device-level non-idealities, we enable a robust execution on memory-centric architectures despite device-level non-idealities and limited computing capability. Overall, this study identifies memory- and storage-centric architectures as a key architectural breakthrough for large-scale, high-speed search acceleration, delivering up to <inline-formula> <tex-math>$gt !!100times $ </tex-math></inline-formula> speedup and <inline-formula> <tex-math>$gt !!40,000times $ </tex-math></inline-formula> improvement in energy efficiency.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 3","pages":"723-737"},"PeriodicalIF":3.8,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148985921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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IEEE Journal on Emerging and Selected Topics in Circuits and Systems Publication Information IEEE关于电路和系统中新兴和选定主题的期刊出版信息

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-09-01 Epub Date: 2026-09-18 DOI: 10.1109/JETCAS.2026.3726572

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A Data-Driven Framework for Modeling Non-Idealities in Analog In-Memory Computing Hardware 模拟内存计算硬件非理想性建模的数据驱动框架

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-09-01 Epub Date: 2026-06-19 DOI: 10.1109/JETCAS.2026.3705427

Athanasios Vasilopoulos;Benedikt Kersting;Julian Büchel;Abu Sebastian;Manuel Le Gallo

{"title":"A Data-Driven Framework for Modeling Non-Idealities in Analog In-Memory Computing Hardware","authors":"Athanasios Vasilopoulos;Benedikt Kersting;Julian Büchel;Abu Sebastian;Manuel Le Gallo","doi":"10.1109/JETCAS.2026.3705427","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3705427","url":null,"abstract":"Analog in-memory computing (AIMC) has gained popularity as an alternative to conventional von Neumann architectures for deep learning inference, offering significant energy and latency advantages. By exploiting the analog properties of memory devices, matrix-vector multiplications can occur within memory arrays, thereby eliminating the movement of weights and associated costs. However, operating in the analog domain introduces a range of non-idealities that hamper the computational precision. These non-idealities can be stochastic or deterministic and are often difficult to characterize analytically due to their complexity and interplay with one another. In this work, we present a data-driven modeling framework that captures the behavior of AIMC hardware using experimental data from the hardware itself. Our approach is grounded in a first-order Taylor approximation of the matrix-vector multiply operation, which leads to the decomposition of the overall error into two components: linear perturbations, mainly stemming from device variability, and non-linear or recurrent residual error, typically induced by circuit-level effects and recurrent noise sources. We demonstrate that this two-model approach can faithfully reproduce the behavior of a real phase-change memory-based AIMC chip. We also show generalization to downstream inference tasks on four different networks, two ResNets for image classification and two LSTMs for character prediction and image captioning, demonstrating that the model predicts the hardware error and task performance in a diverse set of tasks.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 3","pages":"699-709"},"PeriodicalIF":3.8,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148985918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Co-Optimization of Analog Kolmogorov--Arnold Networks for Low-Power Function Approximation in Flexible Electronics 柔性电子低功耗函数逼近模拟Kolmogorov- Arnold网络的协同优化

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-09-01 Epub Date: 2026-06-25 DOI: 10.1109/JETCAS.2026.3707339

Paula Carolina Lozano Duarte;Georgios Zervakis;Mehdi Tahoori;Sani Nassif

{"title":"Co-Optimization of Analog Kolmogorov--Arnold Networks for Low-Power Function Approximation in Flexible Electronics","authors":"Paula Carolina Lozano Duarte;Georgios Zervakis;Mehdi Tahoori;Sani Nassif","doi":"10.1109/JETCAS.2026.3707339","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3707339","url":null,"abstract":"Wearable devices and Internet of Things (IoT) sensors require on-sensor processing of biosignals and environmental data, including computationally demanding operations such as nonlinear activation functions for neural network inference, sensor calibration curves to map raw readings to physical units, and signal preprocessing functions like logarithmic compression and power operations for feature extraction. These functions exhibit significant complexity, often involving transcendental operations and multivariate dependencies that are costly to implement digitally. Analog function approximation provides a power-efficient alternative by performing these computations in the analog domain, thereby reducing the energy overhead associated with analog-to-digital conversion and subsequent digital processing. Flexible Electronics (FE) present a particularly attractive platform for wearable applications due to mechanical flexibility and low-cost fabrication, but impose strict constraints on circuit density and power consumption, making efficient analog implementations critical but challenging. This work introduces Analog Kolmogorov-Arnold Networks (AKANs), developed via hardware–software co-optimization, to approximate these complex multivariate functions accurately under hardware imperfections. Our method incorporates circuit-level error modeling during training and applies pruning at both software and hardware levels to reduce area and power. Validation across multiple benchmarks demonstrates that our proposed pruning methodology not only reduces hardware cost but can also improve approximation accuracy by regularizing spline parameters. Results show up to 55% area and 50% power savings, with average reductions of nearly 30% across datasets, highlighting AKANs as a robust and generalizable framework for low-power analog function approximation in FE.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 3","pages":"738-751"},"PeriodicalIF":3.8,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148985783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Investigating Energy Bounds of Analog Compute-in-Memory With Local Normalization 用局部归一化方法研究模拟内存计算的能量边界

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-09-01 Epub Date: 2026-06-10 DOI: 10.1109/JETCAS.2026.3702517

Brian Rojkov;Shubham Ranjan;Derek Wright;Manoj Sachdev

{"title":"Investigating Energy Bounds of Analog Compute-in-Memory With Local Normalization","authors":"Brian Rojkov;Shubham Ranjan;Derek Wright;Manoj Sachdev","doi":"10.1109/JETCAS.2026.3702517","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3702517","url":null,"abstract":"Modern edge AI workloads demand maximum energy efficiency, motivating the pursuit of analog Compute-in-Memory (CIM) architectures. Simultaneously, the popularity of large language models (LLMs) drives the adoption of low-bit floating-point formats that prioritize dynamic range. However, the conventional direct-accumulation CIM accommodates floating-point values by normalizing them to a shared, widened fixed-point scale. Consequently, hardware resolution is dictated by the input’s dynamic range rather than its precision, and energy consumption is dominated by the ADC. We address this limitation by introducing local normalization for each input, weight, and multiply-accumulate (MAC) output via a <italic>Gain-Ranging MAC (GR-MAC)</i>. Normalization overhead is handled by low-power digital logic, enabling the computationally expensive MAC operation to remain in the energy-efficient low-precision analog regime. Energy modelling shows that adding a gain-ranging stage to the MAC increases the input dynamic range by 4 bits without increasing energy consumption at a 35 dB SQNR standard. Additionally, the ADC resolution requirement becomes invariant to input distribution assumptions, allowing the construction of an upper bound with a 1.5-bit reduction compared to the conventional lower bound. These results establish a pathway to unlocking favourable energy scaling trends in analog CIM for modern AI workloads.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 3","pages":"710-722"},"PeriodicalIF":3.8,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148985919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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In-Memory Computing-Based Ultra-Efficient Massive MIMO Precoding: Memristor Crossbar Circuits, Conductance Mapping Strategies, and Programming Latency Estimation 基于内存计算的超高效大规模MIMO预编码：忆阻交叉电路、电导映射策略和编程延迟估计

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2025-12-29 DOI: 10.1109/JETCAS.2025.3648808

Yu-Xin Zhang;Shaoshi Yang;Yi-Hang Ren;Sheng Chen;Ping Zhang

{"title":"In-Memory Computing-Based Ultra-Efficient Massive MIMO Precoding: Memristor Crossbar Circuits, Conductance Mapping Strategies, and Programming Latency Estimation","authors":"Yu-Xin Zhang;Shaoshi Yang;Yi-Hang Ren;Sheng Chen;Ping Zhang","doi":"10.1109/JETCAS.2025.3648808","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3648808","url":null,"abstract":"Matrix inversion in massive multiple-input multiple-output (MIMO) precoding imposes significant burden on the energy efficiency and processing latency of baseband units. In this paper, we first propose a memristor crossbar based in-memory computing circuit capable of supporting both zero-forcing (ZF) and minimum mean square error (MMSE) precoding. The circuit features a reduced matrix size and enables faster one-step computation without the need for timing control. Secondly, to address the computational inaccuracy caused by the limited conductance range of memristors, we develop an optimized matrix-to-conductance mapping scheme that jointly considers device physical constraints and matrix statistics, achieving over 60% reduction in relative computation error compared with baseline scheme. An associated lightweight circuit enhancement ensures compatibility with practical crossbar architectures, without incurring significant hardware overhead. Thirdly, we establish a memristor programming time model grounded in device-level potentiation and depression dynamics. The analysis yields closed-form expressions for the expected programming time and its upper bound, and is further validated through Monte Carlo simulations, enabling accurate estimation of the system throughput. Simulation results demonstrate that the proposed circuit achieves a bit error rate comparable to that of 64-bit floating-point precoding, while delivering over <inline-formula> <tex-math>$100times $ </tex-math></inline-formula> improvement in both energy and area efficiency compared with the NVIDIA RTX A2000 graphics processing unit (GPU).","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"525-537"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148433140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0