An Implementation of Delay Testable Boundary Scan and Post-Bond Test Results in a 3D IC

Abstract

A defective through-silicon via (TSV) may cause a small delay fault that is difficult to detect using conventional logic testing methods. Testing TSVs used for chip-to-chip interconnection in 3D stacked ICs is a challenging problem. We have proposed a delay testable boundary scan design that has an embedded time-to-digital converter that can measure the timing slack between the test clock and an incoming signal through a TSV. A prototype 3D stacked IC with this delay testable circuit was fabricated using TSVs of various diameters. The measurement results show that the proposed delay testable boundary scan can effectively identify both logic errors that occurred in TSVs with open defects due to a small diameter and outliers in delay through a TSV that have no logic errors.