IEEE Journal on Emerging and Selected Topics in Circuits and Systems最新文献_第3页

IGA-SRAM: A Compact SRAM-Based IMC Engine for Binary/Ternary Deep Neural Networks With ADC-Less and Error-Aware Training Algorithm IGA-SRAM：一种紧凑的基于sram的二/三元深度神经网络IMC引擎，具有无adc和错误感知训练算法

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2026-03-27 DOI: 10.1109/JETCAS.2026.3678317

Shin-Uk Kang;Dong-Hyun Lee;Min-Gwon Song;Mingoo Seok;Min-Seong Choo

{"title":"IGA-SRAM: A Compact SRAM-Based IMC Engine for Binary/Ternary Deep Neural Networks With ADC-Less and Error-Aware Training Algorithm","authors":"Shin-Uk Kang;Dong-Hyun Lee;Min-Gwon Song;Mingoo Seok;Min-Seong Choo","doi":"10.1109/JETCAS.2026.3678317","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3678317","url":null,"abstract":"This work presents a compact 6T SRAM-based analog in-memory computing (A-IMC) macro for energy-efficient inference of binary and ternary neural networks (BNNs/TNNs). While conventional A-IMC architectures suffer from significant area and power overheads due to high-resolution analog-to-digital converters (ADCs), we propose an ADC-less computing scheme based on 1-bit sense amplifiers (SAs), supported by a novel training algorithm that mitigates quantization-induced performance degradation. To maintain hardware simplicity, we adopt a compact 6T bitcell structure and introduce dual wordlines (WLs) for efficient ternary input encoding. We further propose impulse Gaussian approximation (IGA), a differentiable quantization surrogate that enables stable and accurate gradient backpropagation in the presence of 1-bit partial sum quantization. Additionally, we introduce an error-aware training (EAT) method that leverages measured partial-sum (PS) error statistics from silicon to inject gradually increasing noise in the training phase, effectively compensating for hardware-induced variations. Fabricated in a 65 nm CMOS GP process, the proposed <inline-formula> <tex-math>$128times 128$ </tex-math></inline-formula> A-IMC macro achieves 47.06 TOPS/mm2 and CIFAR10 accuracy of 86.89% under 1.2/0.7 V operating voltages with ResNet20.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"276-288"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148511866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Guest Editorial In-Memory Computing (IMC): From Technology to Applications 内存计算（IMC）：从技术到应用

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2026-06-15 DOI: 10.1109/JETCAS.2026.3696794

Alberto Bosio;Deliang Fan;Xueqing Li;Leticia Maria Bolzani Poehls

引用次数: 0

Complementary Reconfigurable Field-Effect Transistor-Based Hybrid 6T SRAM Cell as a Multibit Dot-Product Engine In-Memory-Computing 基于互补可重构场效应晶体管的混合6T SRAM单元在内存计算中的多比特点积引擎

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2026-03-04 DOI: 10.1109/JETCAS.2026.3690134

Saroj Satapathy;Juhan Ahn;Jaydeep Kulkarni

{"title":"Complementary Reconfigurable Field-Effect Transistor-Based Hybrid 6T SRAM Cell as a Multibit Dot-Product Engine In-Memory-Computing","authors":"Saroj Satapathy;Juhan Ahn;Jaydeep Kulkarni","doi":"10.1109/JETCAS.2026.3690134","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3690134","url":null,"abstract":"In-Memory Computing holds the promise to break the memory wall challenge; however, established memory device scaling cannot keep pace with growing architectural demands. We propose a complementary reconfigurable field effect transistor (CRFET) based hybrid 6T SRAM bitcell that holds potential for IMC architectures. established memory device scaling cannot keep pace with growing architectural demands. CRFET devices can be configured as n-type or p-type transistors during runtime using an additional programmable gate (PG) bias. Leveraging its CMOS compatibility, we combine conventional MOS transistors with CRFET transistors to propose a hybrid 6T bitcell. We exploit the current tuning capability of the CRFET device pass gate in the bitcell to achieve the multibit dot-product computations. We analyze and discuss the area efficiency through proposed mask designs, better noise margin, and energy efficiency through simulation using a Verilog-A-based spice model developed with the help of the Technology Computer-Aided Design (TCAD) simulations of a 7nm equivalent process design kit. We also demonstrate the robustness of the dot product engine (DPE) IMC in terms of output current and voltage characteristics, bitline non-linearities of multiple row arrays, and error percentage. The analysis shows that without area penalties compared to a conventional 6T memory array, it provides 24% better read noise margin and 18% average energy per operation efficiency versus conventional multibit DPE IMC implementations.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"180-187"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148512544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

NMPHDC: A 12-nm Reconfigurable Multi-Port SRAM-Based Near-Memory Hyperdimensional Computing Architecture NMPHDC：一种基于12nm可重构多端口sram的近存储器超维计算架构

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2026-02-24 DOI: 10.1109/JETCAS.2026.3667611

Md Rubel Sarkar;Isha Makwana;Umme Hani Irin;Md Minhajul Azmir;Shirazush Salekin Chowdhury;Jinhui Wang;Yang Yi

{"title":"NMPHDC: A 12-nm Reconfigurable Multi-Port SRAM-Based Near-Memory Hyperdimensional Computing Architecture","authors":"Md Rubel Sarkar;Isha Makwana;Umme Hani Irin;Md Minhajul Azmir;Shirazush Salekin Chowdhury;Jinhui Wang;Yang Yi","doi":"10.1109/JETCAS.2026.3667611","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3667611","url":null,"abstract":"Hyperdimensional Computing (HDC) is a brain-inspired computing paradigm that represents information using high-dimensional vectors, referred to as hypervectors (HVs), enabling inherent robustness to noise and efficient learning on resource-constrained platforms. In this work, we present NMPHDC, a reconfigurable multi-port (MP) SRAM-based logic-near-memory (LnM) HDC architecture that supports on-chip training and inference. The proposed design is configurable across multiple HV dimensions, including 256, 512, and 1024 bits, enabling flexibility across diverse workloads. A lightweight custom LnM block enables LnM execution of key HDC operations, including XOR for binding and majority (MAJ) for bundling, significantly reducing data movement overhead. In addition, we propose a custom on-chip training algorithm and integrate a dedicated on-chip random number generator (RNG) to strengthen training security through locally generated HVs. A centralized HDC controller orchestrates dataflow, computation, training, and testing with seamless configurability. Implemented in GlobalFoundries (GF) 12 nm low-power (LP) FinFET technology, NMPHDC occupies 1.25 mm2, consumes ~0.72 mW in standby and ~19.7 mW at 100 MHz, and achieves classification accuracies of 93.33%, 25.75%, 72.62%, and 75.18% on the ECG5000, CIFAR-10, MNIST, and ISOLET datasets, respectively.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"412-426"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148433227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A CMOS Compatible Energy Efficient 6T NV-SRAM-Based Accelerator Employing Binary Neural Networks in 22 nm FDSOI Technology 采用二进制神经网络的22纳米FDSOI技术的CMOS兼容节能6T nv - sram加速器

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2025-12-22 DOI: 10.1109/JETCAS.2025.3646841

Umme Hani Irin;Md Minhajul Azmir;Md Rubel Sarkar;Chence Yang;Geng Yuan;Yang Yi;Jinhui Wang

{"title":"A CMOS Compatible Energy Efficient 6T NV-SRAM-Based Accelerator Employing Binary Neural Networks in 22 nm FDSOI Technology","authors":"Umme Hani Irin;Md Minhajul Azmir;Md Rubel Sarkar;Chence Yang;Geng Yuan;Yang Yi;Jinhui Wang","doi":"10.1109/JETCAS.2025.3646841","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3646841","url":null,"abstract":"In this paper, a CMOS compatible non-volatile 6T-SRAM (NV-SRAM) based accelerator is proposed using a Compute-In-Memory (CIM) and Binary Neural Network (BNN) architecture to scale the persistent and energy-efficient on-chip storage for Edge AI systems. The proposed NV-SRAM facilitate reliable on-chip storage for weights and feature maps without off-chip reloading, providing data persistence and security as well as reducing information lost. As a case study, the proposed accelerator utilizes a (<inline-formula> <tex-math>$400times 200$ </tex-math></inline-formula>) NV-SRAM array to enable binarized <inline-formula> <tex-math>$20times 20$ </tex-math></inline-formula> MNIST image processing and efficient mapping of 400-bit activation vectors with the assistance of the specially designed peripheral circuits. Especially, on-chip in-memory XNOR and pop-count operations reduce inter-chip data movement, and as a result, lead to an energy-efficient processing. The design is implemented and validated in 22 nm FDSOI Technology with 0.8 V power supply to achieve throughput: 8 TOPS (8000 GOPS) and 200 TOPS/W and inference accuracy: 96.85% with MLP for MNIST, showing high energy efficiency, scalable parallelism, and small silicon area. As compared to state-of-the-art, the proposed NV-SRAM based BNN accelerator combines non-volatility, high computational throughput, and CMOS compatibility, making it a strong candidate for Internet of Things (IoT), robotics, autonomous sensors, and embedded vision in Edge AI platforms.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"262-275"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148509922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

TDC-CiM: Time-to-Digital Converter-Based Resonant Compute-in-Memory for INT8 CNNs With Layer-Optimized SRAM Mapping TDC-CiM：基于时间-数字转换器的谐振内存计算INT8 cnn与层优化SRAM映射

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2025-12-17 DOI: 10.1109/JETCAS.2025.3645585

Dhandeep Challagundla;Ignatius Bezzam;Riadul Islam

{"title":"TDC-CiM: Time-to-Digital Converter-Based Resonant Compute-in-Memory for INT8 CNNs With Layer-Optimized SRAM Mapping","authors":"Dhandeep Challagundla;Ignatius Bezzam;Riadul Islam","doi":"10.1109/JETCAS.2025.3645585","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3645585","url":null,"abstract":"In recent years, Compute-in-memory (CiM) architectures have emerged as a promising solution for deep neural network (NN) accelerators. Multiply-accumulate (MAC) is considered a <italic>de facto unit operation in NNs. By leveraging the inherent parallel processing capabilities of CiM, NNs that require numerous MAC operations can be executed more efficiently. This is further facilitated by storing the weights in SRAM, reducing the need for extensive data movement and enhancing overall computational speed and efficiency. Traditional CiM architectures execute MAC operations in the analog domain, employing an Analog-to-Digital converter (ADC) to convert the analog MAC values into digital outputs. However, these ADCs introduce a significant increase in area and power consumption, as well as introduce non-linearities. This work proposes a resonant time-domain compute-in-memory (TDC-CiM) architecture that eliminates the need for an ADC by using a time-to-digital converter (TDC) to digitize analog MAC results with lower power and area cost. A dedicated 8T SRAM cell enables reliable bitwise MAC operations, while the readout uses a 4-bit TDC with pulse-shrinking delay elements, achieving 1 GS/s sampling with a power consumption of only 1.25 mW. In addition, a weight-stationary data mapping strategy combined with an automated SRAM macro selection algorithm enables scalable and energy-efficient deployment across CNN workloads. Evaluation across six CNN models shows that the algorithm reduces inference energy consumption by up to <inline-formula> <tex-math>$8times $ </tex-math></inline-formula> when scaling SRAM size from 32 KB to 256 KB, while maintaining minimal accuracy loss after quantization. The feasibility of the proposed architecture is validated on an 8 KB SRAM memory array using TSMC 28 nm technology. The proposed TDC-CiM architecture demonstrates a throughput of 320 GOPS with an energy efficiency of 38.46 TOPS/W.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"227-238"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148511872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Coalesced Tensor Reduction Architecture for Scalable All-Bank PIM Execution 面向可伸缩全银行PIM执行的合并张量约简体系结构

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2026-01-26 DOI: 10.1109/JETCAS.2026.3657823

Taehyung Park;Hyuk-Jae Lee;Chae Eun Rhee

{"title":"A Coalesced Tensor Reduction Architecture for Scalable All-Bank PIM Execution","authors":"Taehyung Park;Hyuk-Jae Lee;Chae Eun Rhee","doi":"10.1109/JETCAS.2026.3657823","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3657823","url":null,"abstract":"The embedding layer in deep learning recommendation models (DLRM) is highly memory-bound and exhibits skewed, irregular access patterns. These characteristics lead to severe load imbalance and performance bottlenecks in processing in memory (PIM) architectures. We propose TRAM (Two-level Reduction Accelerator for Memory), a heterogeneous accelerator that integrates High Bandwidth Memory based PIM architecture (HBM-PIM) with conventional dual in-line memory modules (DIMMs) to accelerate batched embedding vector reductions. TRAM reduces redundant hot-vector accesses and employs a host-side scheduling mechanism that overlaps bank-PIM operations inside DRAM banks with logic-PIM operations, where processing units are located in the buffer die. This overlap eliminates command-bandwidth stalls and compute-bound delays. In addition, metadata-aware optimizations reduce row/column access overhead by reusing contiguous address patterns within each bank. Evaluation on six recommendation datasets and three embedding dimensions demonstrates that TRAM achieves up to <inline-formula> <tex-math>$2.8times $ </tex-math></inline-formula> speedup and <inline-formula> <tex-math>$3.0times $ </tex-math></inline-formula> energy reduction compared to state-of-the-art heterogeneous memory systems, while preserving full compatibility with the standard DRAM interface.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"389-402"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148512283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

JADE: Joint Architecture-Dataflow Exploration for LLM Inference on Heterogeneous In- and Near-Memory Computing Systems 面向异构内存和近内存计算系统的LLM推理联合架构-数据流探索

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2026-03-30 DOI: 10.1109/JETCAS.2026.3679018

Yimin Wang;Zhen Wu;Yue Jiet Chong;Xuanyao Fong

{"title":"JADE: Joint Architecture-Dataflow Exploration for LLM Inference on Heterogeneous In- and Near-Memory Computing Systems","authors":"Yimin Wang;Zhen Wu;Yue Jiet Chong;Xuanyao Fong","doi":"10.1109/JETCAS.2026.3679018","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3679018","url":null,"abstract":"Large Language Model (LLM) inference challenges memory/computing organization and dataflow optimization on traditional hardware stacks due to its various attention mechanisms and autoregressive structure. In-memory computing (IMC) and near-memory computing (NMC) architectures have emerged as potential solutions to reduce the memory burden in LLMs. However, efficient LLM orchestration on IMC/NMC, as well as dedicated IMC/NMC architecture optimization, are interrelated, encompassing a hardware-software co-design space of a myriad of parameters, which still remains largely underexplored. This work provides a joint architecture-dataflow exploration (JADE) framework that covers both architectural factors on computing/memory/communication, and algorithmic factors on LLM dataflow. We identify key configurations in four categories: computing and memory organization, interconnection topology, matrix multiplication (MM) unrolling and mapping, and attention mechanism. A unified MM representation enables flexible unrolling and mapping on various architectural organizations. Dataflow is routed based on the collective communication patterns inherent in the distributed LLMs and the features of common topologies. Finally, case studies show the design tradeoffs between key design options and provide insights into both homogeneous and heterogeneous IMC/NMC design for LLMs.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"378-388"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148514136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Page-Buffer and Fail-Bit Counter-Based In-Memory Computing Platform for 3-D NAND Flash Memory 基于页面缓冲和故障位计数器的三维NAND闪存内存计算平台

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2026-01-30 DOI: 10.1109/JETCAS.2026.3659465

Wen-Jer Tsai;Chun-Chang Lu;Ting-En Hsieh;Tao-Cheng Lu;Kuang-Chao Chen;Tuo-Hung Hou;Chih-Yuan Lu

引用次数: 0

Voltage-Summation-Based Compute-in-Memory SRAM Macro With Input-Bit and Synaptic-Bit Slicing 具有输入位和突触位切片的基于电压求和的内存SRAM宏

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2026-04-29 DOI: 10.1109/JETCAS.2026.3688959

Jung Nam Kim;Yong Woo Kim;Won Joo Lee;Minsuk Koo;Yoon Kim

{"title":"Voltage-Summation-Based Compute-in-Memory SRAM Macro With Input-Bit and Synaptic-Bit Slicing","authors":"Jung Nam Kim;Yong Woo Kim;Won Joo Lee;Minsuk Koo;Yoon Kim","doi":"10.1109/JETCAS.2026.3688959","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3688959","url":null,"abstract":"Compute-in-memory (CIM) technology has emerged as a promising solution for energy-efficient matrix-vector multiplication (MVM), addressing the inherent limitations of von Neumann architecture. However, conventional Kirchhoff’s current law based CIM technologies suffer from drawbacks such as <italic>I-R drop and energy inefficiency due to static current flow over a wide dynamic range. This paper introduces an energy-efficient and <italic>I-R drop-free CIM architecture based on capacitive coupling principle. Synaptic weights represented in 4-bit two’s complement format are stored in SRAM-based 9T1C bit-cells. The architecture utilizes input-bit slicing method to perform MVM operations without the need for multi-bit digital-to-analog converters (DACs), significantly improving energy efficiency. A neuron circuit employs successive integration and rescaling (SIR) process to handle input-bit slicing encoded analog MVM results efficiently. The fabricated 16 kb, 28-nm prototype chip achieves an energy efficiency of 230 TOPS/W and a throughput of 32.19 GOPS for MVM operation with 4-bit resolution input and synaptic weights at a 100 MHz clock frequency. Even with ADC-induced analog variability, the proposed architecture achieves 90.64% and 97.99% inference accuracy for single-layer and multi-layer networks on the MNIST dataset, and 86.25% on CIFAR-10, validating its effectiveness and practical viability for low-power edge inference in complex workloads.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"218-226"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148511164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0