IEEE Journal on Emerging and Selected Topics in Circuits and Systems最新文献_第4页

AM5: Bulk Logic-in-Memory Using MRAM NAND Crossbar AM5：使用MRAM NAND Crossbar的内存中批量逻辑

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2026-03-01 DOI: 10.1109/JETCAS.2026.3689530

Cristhopher Mosquera;Esteban Garzón;Marco Lanuzza;Adam Teman;Leonid Yavits

{"title":"AM5: Bulk Logic-in-Memory Using MRAM NAND Crossbar","authors":"Cristhopher Mosquera;Esteban Garzón;Marco Lanuzza;Adam Teman;Leonid Yavits","doi":"10.1109/JETCAS.2026.3689530","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3689530","url":null,"abstract":"Application domains, such as machine learning and big data analytics, impose significant computational challenges to contemporary Von Neumann architectures. To address this issue, logic-in-memory (LiM) has been raised as a promising alternative that targets computing within memory arrays, aimed at alleviating the memory wall, optimizing data transfer, and enabling massive parallelism. Spin-transfer torque magnetic tunnel junction (STT-MTJ) based memory is an emerging memory technology that enables efficient processing using memory. This paper proposes AM5, a novel LiM architecture leveraging MRAM NAND crossbar technology to support in-memory arithmetic operations efficiently. The proposed LiM scheme is designed using a commercial 28 nm process node and a Verilog-A-based double-barrier MTJ compact model. Evaluation results show that AM5 consumes about 98 fJ/40.7 fJ/DMTJ per evaluation/write cycle (4.2-4.4 ns/1.9 ns). Additionally, the proposed architecture proposes an in-situ error correction mechanism to mitigate variability, yielding reliable arithmetic operations. These findings show better energy (~6 <inline-formula> <tex-math>$times $ </tex-math></inline-formula> lower, on average) and competitive latency (~1.3 <inline-formula> <tex-math>$times $ </tex-math></inline-formula> faster, on average) figures of AM5 compared to other LiM designs based on MTJ-based technology. When used as a LiM unit to perform inference in adder attention Vision Transformer networks, AM5 consumes about one-tenth of the energy required by a processor-centric unit.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"203-217"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11503235","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148512320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Compressed High-Order Ising Machines 压缩高阶成型机

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2026-03-04 DOI: 10.1109/JETCAS.2026.3690185

George Higgins Hutchinson;Tinish Bhattacharya;Dongseok Kwon;Fabian Böhm;Giacomo Pedretti;Thomas Van Vaerenbergh;Ray Beausoleil;Arne Heittmann;John Paul Strachan;Dmitri Strukov

{"title":"Compressed High-Order Ising Machines","authors":"George Higgins Hutchinson;Tinish Bhattacharya;Dongseok Kwon;Fabian Böhm;Giacomo Pedretti;Thomas Van Vaerenbergh;Ray Beausoleil;Arne Heittmann;John Paul Strachan;Dmitri Strukov","doi":"10.1109/JETCAS.2026.3690185","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3690185","url":null,"abstract":"We propose a “compressed” memory-centric high-order Ising machine (IM) architecture for solving hard optimization problems, featuring guaranteed log-linear hardware area scaling with the number of variables. The key feature of the proposed architecture is a novel unit cell for coupling spins, more complex than comparable IM cells. This unit cell keeps a local copy of a specific spin value, which can be updated when receiving a message of that variable’s change on a common bus. The unit cell also includes circuitry for computing a high-degree product that contributes to the partial derivative of another spin. Because the position of the coupling term in the coupling matrix array is no longer determined by the row and column indices of the constituent spins, we observe up to 75% unit cell utilization in relevant benchmarks. The compressed architecture is especially useful for Boolean satisfiability (SAT) problems, the focus of this study, in that it enables implementation of an “enhanced” Ising machine architecture that preserves clause-variable membership information of the mapped problem. K-SAT problems can be embedded in their native form, allowing such problems to be solved not only by conventional simulated-annealing-based high-order Ising machine dynamics but also with more competitive heuristics inspired by the state-of-the-art SAT solving algorithms. A detailed circuit architecture and design automation methods for mapping SAT problems are presented, and post-layout SPICE simulations are performed. Modeling results for solving random uniform problems show that even the simplest, sequential version of the proposed approach, in which only one spin is flipped at a time, is significantly faster and has comparable energy efficiency while being almost an order of magnitude more compact than previously reported work on combinatorial optimization solvers.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"577-592"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148433203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Journal on Emerging and Selected Topics IEEE新兴和选定主题杂志

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2026-06-15 DOI: 10.1109/JETCAS.2026.3696785

引用次数: 0

Monolithically Integrated Transimpedance Accumulators for Analog In-Memory Computing Based on Dual-Gate Metal-Oxide TFTs 基于双栅金属氧化物tft的内存模拟计算单片集成跨阻累加器

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2026-04-27 DOI: 10.1109/JETCAS.2026.3688129

Tengteng Lei;Jiayi Mao;Yushen Hu;Man Wong

{"title":"Monolithically Integrated Transimpedance Accumulators for Analog In-Memory Computing Based on Dual-Gate Metal-Oxide TFTs","authors":"Tengteng Lei;Jiayi Mao;Yushen Hu;Man Wong","doi":"10.1109/JETCAS.2026.3688129","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3688129","url":null,"abstract":"Analog in-memory computing (IMC) performing multiply-accumulate (MAC) operations demand not only synaptic multipliers but also high-performance current accumulators. With the channel region of a dual-gate (DG) thin-film transistor (TFT) sandwiched between two overlapping gate electrodes, the threshold voltage referred to one gate can be modulated by the bias applied on the other. Enabled by the tunability of their threshold voltages and ultra-low leakage current, DG TFTs have been deployed as synapses in artificial neural networks (ANNs). With a transimpedance of ~170 k<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>, an accumulation current range of <inline-formula> <tex-math>$sim!55~mu $ </tex-math></inline-formula>A and tunable lower/upper bounds ranging from −55/<inline-formula> <tex-math>$0~mu $ </tex-math></inline-formula>A to 0/<inline-formula> <tex-math>$55~mu $ </tex-math></inline-formula>A, a transimpedance current accumulator (TIA) with common-gate input stage incorporating DG TFTs has been presently designed, fabricated and characterized. Benefiting also from the high differential output resistance of a DG TFT and a gain-boosting stage, the TIA offers a relatively small input impedance of ~5 k<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>. An ANN featuring monolithically integrated TIAs alongside a synaptic array is constructed, and the utility of this integrated architecture is successfully demonstrated with the classification of 16 binary images.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"607-616"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148433224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Algorithm-Hardware Implications of Softmax Approximations for In-Memory Computing-Based LLM Accelerators 基于内存计算的LLM加速器的Softmax近似的算法-硬件含义

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2026-02-06 DOI: 10.1109/JETCAS.2026.3661247

Jan Finkbeiner;Sebastian Siegel;Chirag Sudarshan;Yuankang Zhao;John Paul Strachan;Emre Neftci

{"title":"Algorithm-Hardware Implications of Softmax Approximations for In-Memory Computing-Based LLM Accelerators","authors":"Jan Finkbeiner;Sebastian Siegel;Chirag Sudarshan;Yuankang Zhao;John Paul Strachan;Emre Neftci","doi":"10.1109/JETCAS.2026.3661247","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3661247","url":null,"abstract":"As large language models (LLMs) continue to scale in both size and particularly in sequence length, the softmax-attention mechanism of the underlying transformer architecture has emerged as a critical bottleneck. While in-memory computing (IMC) based architectures offer efficient acceleration for vector-matrix multiplications (VMMs), integrating softmax remains challenging due to its computational complexity. This work presents a comprehensive analysis of softmax approximations and softmax precision requirements in modern LLMs spanning model sizes from 125M to 405B parameters across several natural language processing (NLP) benchmarks. Based on these findings, we present an IMC-optimized reformulation of softmax for attention that results in negligible accuracy degradation, Including: 1) transformation of complexity from sequence-length-dependency to the much smaller attention head dimension; and 2) merging of softmax components within the adjacent IMC’s VMM operations. We present both digital and analog implementations. Our digital approach reduces area overhead to <inline-formula> <tex-math>$mathrm {81.2~mu text {m}^{2}}$ </tex-math></inline-formula> and energy to 0.69 pJ per input-output pair, resulting in more than <inline-formula> <tex-math>$20 times $ </tex-math></inline-formula> lower energy-delay-area product compared to state-of-the-art. Our analog implementation achieves <inline-formula> <tex-math>$mathrm {37.1~mu text {m}^{2}}$ </tex-math></inline-formula> and 0.33 pJ by leveraging a spike-based encoding. These results highlight the importance of rethinking softmax computation for IMC to enable scalable transformer accelerators.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"483-499"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11372754","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148433268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hierarchical Memristor-Based IMPLY Comparator Architecture for In-Memory Computing 基于分层忆阻器的内存计算的隐式比较器结构

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2026-02-03 DOI: 10.1109/JETCAS.2026.3660720

Yunlai Zhu;Yong Zhang;Ying Yang;Ke Wang;Xiaoling Wu;Tao Jiang;Chaotong Xie;Zhongren Ye;Haotian Tang;Zhan Chen;Liang Yao;Zuyu Xu;Zhe Feng;Lihua Xu;Wendong Lu;Zuheng Wu;Yuehua Dai

{"title":"Hierarchical Memristor-Based IMPLY Comparator Architecture for In-Memory Computing","authors":"Yunlai Zhu;Yong Zhang;Ying Yang;Ke Wang;Xiaoling Wu;Tao Jiang;Chaotong Xie;Zhongren Ye;Haotian Tang;Zhan Chen;Liang Yao;Zuyu Xu;Zhe Feng;Lihua Xu;Wendong Lu;Zuheng Wu;Yuehua Dai","doi":"10.1109/JETCAS.2026.3660720","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3660720","url":null,"abstract":"To address the inherent bottlenecks of comparison latency and energy efficiency caused by the separation of computation and storage in the von Neumann architecture, this study proposes a memristor-based modular hierarchical tree comparator that employs implication (IMPLY) logic. The proposed architecture performs parallel bit-wise comparisons, generating ternary outputs (“>”, “<”, “=”) that are aggregated through a balanced binary tree structure. This approach reduces comparison latency from linear to logarithmic scaling with bit width. A dedicated sign-bit processing module enables flexible support for both signed and unsigned data formats. Circuit simulations demonstrate that, compared with existing memristor-based IMPLY logic unsigned comparators, the proposed unsigned comparator achieves a 7.8%–21.9% energy reduction for unsigned comparisons, while the proposed signed comparator not only extends the functionality but also achieves a 6.7%–15.1% reduction in energy consumption compared with unsigned comparators of the same bit-width. The architecture also achieves significant latency and Figure of Merit (FoM) improvements over memristor-aided logic and IMPLY-based designs, outperforming existing approximate computing approaches at large bit widths. Validation in image processing applications confirms the architecture’s potential for high-throughput, low-power tasks, establishing a promising design paradigm for efficient in-memory comparison.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"302-311"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148513952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Efficient Neural Architecture Search With CIM-Based Architecture 基于cim的高效神经结构搜索

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2026-03-17 DOI: 10.1109/JETCAS.2026.3674914

Shixin Zhao;Bing Li;Hui Li;Kai Zhang;Songyun Qu;Xiaohan Ma;Mengdi Wang;Yinhe Han;Ying Wang

{"title":"Efficient Neural Architecture Search With CIM-Based Architecture","authors":"Shixin Zhao;Bing Li;Hui Li;Kai Zhang;Songyun Qu;Xiaohan Ma;Mengdi Wang;Yinhe Han;Ying Wang","doi":"10.1109/JETCAS.2026.3674914","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3674914","url":null,"abstract":"One-shot Neural Architecture Search (NAS) has demonstrated significant improvements over human-designed neural networks in accuracy and hardware-specific metrics such as power consumption and latency. Employing a weight-sharing strategy avoids the need to train all architectures from scratch, providing efficient neural architecture design. However, due to the continuous sampling of multiple sub-networks during the search process in one-shot NAS, retrieving supernet parameters for sub-network evaluations generates a significant amount of data transfer. Additionally, sub-network inference still involves considerable computation, resulting in one-shot NAS requiring hundreds of GPU hours. To address these challenges, we introduce a ReRAM-based Computing-In-Memory (CIM) accelerator that leverages the inherent advantages of ReRAM technology. This accelerator enables in-situ computation for sampled sub-networks and mitigates memory access issues. Despite this advancement, the computational demands of one-shot NAS still need to be overcome. To minimize the overall overhead, we present a novel scheduling method that strategically executes groups of sub-networks within CIM arrays, enhancing concurrency and minimizing redundant computations among shared operators. Additionally, we introduce a CIM-optimized one-shot NAS algorithm that selectively samples sub-networks with common operators during each iteration, further reducing redundant computations. Experimental results show that our CIM NAS accelerator achieves a <inline-formula> <tex-math>$196.6times $ </tex-math></inline-formula> speedup and <inline-formula> <tex-math>$1200times $ </tex-math></inline-formula> energy savings compared to the CPU+GPU baseline.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"289-301"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148514128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Lossless, Reconfigurable FP8 Compute-in-Memory Accelerator With Domino Logic-Based In-Memory Multiplication and Sign-Group Aggregation for Transformers 基于Domino逻辑的内存乘法和符号组聚合的无损可重构FP8内存计算加速器

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2026-02-02 DOI: 10.1109/JETCAS.2026.3660129

Dongrui Li;Anh Tuan Do;Bo Wang

{"title":"A Lossless, Reconfigurable FP8 Compute-in-Memory Accelerator With Domino Logic-Based In-Memory Multiplication and Sign-Group Aggregation for Transformers","authors":"Dongrui Li;Anh Tuan Do;Bo Wang","doi":"10.1109/JETCAS.2026.3660129","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3660129","url":null,"abstract":"Efficient on-device execution of transformer-based models (TBMs) requires specialized hardware acceleration. Yet, stringent memory and power constraints hinder the deployment of TBMs on edge platforms, necessitating aggressively quantized models to maintain energy efficiency. FP8 data types (E5M2/E4M3) provide a compelling 8-bit quantization alternative to FP16/BF16/FP32, enabling more efficient MAC computations. However, most existing FP CIM accelerators rely on serialized pre-alignment, incurring significant accuracy degradation and energy overhead. To overcome these limitations, we propose a novel FP8 CIM accelerator that integrates 1) bit-parallel, reconfigurable, Domino-logic-based FP8 multipliers with <inline-formula> <tex-math>$3.2times $ </tex-math></inline-formula> improved energy-delay-product to support dual FP8 formats, 2) post-alignment, reconfigurable sign-group aggregation units to enable efficient and precision-preserving computing, and 3) a lossless mantissa mapping scheme to facilitate seamless higher-/mixed-precision MAC operations. Fabricated in 40 nm CMOS, our test chip achieves macro-level energy efficiencies of 42.13 TFLOPS/W for E5M2 and 38.23 TFLOPS/W for E4M3, respectively. Moreover, it delivers a system energy efficiency of 9.78 TFLOPS/W and a system compute density of 0.047 TOPS/mm<sup>2</sup>, <inline-formula> <tex-math>$4.3times $ </tex-math></inline-formula> and up to <inline-formula> <tex-math>$1.42times $ </tex-math></inline-formula> higher, respectively, compared to the state-of-the-art TBM-oriented CIM accelerator. These results demonstrate that the proposed CIM circuitry provides a highly energy-efficient solution for on-chip transformer acceleration while maintaining computational accuracy.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"455-468"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148433209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

MoF-LoRA: Mixture of Low-Rank Fault-Tolerant Experts for RRAM-Based In-Memory Computing MoF-LoRA：基于ram的内存计算低阶容错专家的混合

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2026-01-19 DOI: 10.1109/JETCAS.2026.3655242

Soyed Tuhin Ahmed;Eduardo Ortega;Patrick Xiao;Ben Feinberg;Christopher H. Bennett;Matthew J. Marinella;Krishnendu Chakrabarty

{"title":"MoF-LoRA: Mixture of Low-Rank Fault-Tolerant Experts for RRAM-Based In-Memory Computing","authors":"Soyed Tuhin Ahmed;Eduardo Ortega;Patrick Xiao;Ben Feinberg;Christopher H. Bennett;Matthew J. Marinella;Krishnendu Chakrabarty","doi":"10.1109/JETCAS.2026.3655242","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3655242","url":null,"abstract":"Resistive random-access memory (RRAM)-based in-memory computing (R-IMC) architectures achieve energy efficiency by avoiding data movement for matrix-vector computation. However, R-IMC suffers from reliability challenges, such as programming errors, conductance drift, and stuck-at faults, which introduce noise and degrade performance. Several approaches have been proposed in the literature to enhance reliability; however, these solutions are limited to a few specific types of non-idealities, and they cannot be applied to large models, pre-trained models, or R-IMC architectures without introducing considerable computation and memory overhead. We propose a design-time solution that uses a mixture of fault-tolerant experts by adapting pre-trained models via low-rank adaptation. We train non-idealities-specific experts, which are merged with the base weights before mapping, ensuring no added cost yet reliable R-IMC inferencing. For a range of vision and language tasks with transformer models, we show that our approach improves inferencing accuracy by up to 76% under a mixture of non-idealities, enabling reliable mapping and inferencing of vision–language models with no additional cost at runtime.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"563-576"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148433346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Publication Information IEEE关于电路和系统中新兴和选定主题的期刊出版信息

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2026-06-15 DOI: 10.1109/JETCAS.2026.3696787

引用次数: 0