IEEE Journal on Emerging and Selected Topics in Circuits and Systems最新文献

{"title":"High-Speed MAGIC-Based Exact and Approximate Adders for In-Memory Computing","authors":"Nandit Kaushik;Fabian Seiler;Nima Amirafshar;Nima TaheriNejad;Srinivasu Bodapati","doi":"10.1109/JETCAS.2026.3669637","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3669637","url":null,"abstract":"As data-intensive applications such as Machine Learning (ML) continue to drive escalating computational demands, traditional approaches face increasing difficulty in meeting performance requirements. Memory-centric computing has emerged as a promising paradigm by enabling computations to be performed directly within memory, thereby reducing the latency and energy overhead associated with data movement. Approximate computing (AxC) offers another complementary approach, improving performance metrics such as speed at the cost of reduced accuracy. In this work, the stateful Memristor Aided loGIC (MAGIC) is employed to integrate these paradigms for the design of exact and approximate full adders, forming the basis for modern computing tasks. The proposed exact MAGIC-based Full Adder (MFA), implemented on a parallel architecture, achieves a 27.7% to 65.7% reduction in latency compared to State-of-the-Art (SoA) exact MAGIC adder, with a minimal <inline-formula> <tex-math>$mathbf {4 times 5}$ </tex-math></inline-formula> crossbar footprint. Additionally, a novel approximation methodology is proposed, yielding three MAGIC-based Approximate Full Adder (MAFA) designs, which are integrated with the MFA to construct Ripple Carry Adders (RCAs) with varying degrees of approximation. Compared to the best existing exact MAGIC adder the MAFA designs improve latency by 37.3% to 68.6%, require 19.6% to 49.6% less area, and reduce the energy consumption by 20% to 54.4%. We evaluated the proposed MAFA designs across four image-processing applications. The results demonstrate that they achieve acceptable output quality comparable to the best SoA approximate memristive adders, while reducing latency by up to 78% and improving energy efficiency by up to <inline-formula> <tex-math>$35times $ </tex-math></inline-formula>. Evaluation on CNN models, including ResNet, DenseNet, and VGG families, shows that MAFA-based adders incur a slight accuracy loss while significantly improving latency and energy efficiency, highlighting their suitability for ML workloads.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"312-326"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148513072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reconfigurable In-Memory Computing Using Standard 6T SRAM for BCAM, TCAM, Similarity Indexing, and Logic-in-Memory Operations","authors":"Eman Hassan;K. M. Shadid Hassan;Shaymaa Elshahaby;Baker Mohammad","doi":"10.1109/JETCAS.2026.3690750","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3690750","url":null,"abstract":"In-memory computing (IMC) has emerged as a promising paradigm to overcome the von Neumann bottleneck by performing computations directly within memory, thereby reducing data movement and improving energy efficiency. Among various memory technologies, SRAM-based Content Addressable Memories (CAMs) stand out for their high-speed operation and compatibility with CMOS technology. Prior SRAM-CAM IMC architectures typically rely on modified 8T/10T cells or suffer from trade-offs between accuracy, stability, area, and energy, limiting widespread adoption. To address these limitations, this work introduces a reconfigurable SRAM <italic>(R-SRAM)</i> architecture built entirely from unmodified push-rule 6T cells, preserving foundry compatibility while extending functionality beyond existing designs. The proposed macro unifies conventional SRAM, Binary and Ternary CAM (BCAM/TCAM), similarity-index computation, and in-memory bitwise logic (AND, NOR, INV) within a single array. Comprehensive post-layout simulations with Monte Carlo statistical analysis in 22 nm FDSOI validate the design’s functionality, robustness, and performance. Results show 0.44 fJ/bit energy for BCAM/TCAM search, minimal area overhead, and stable cell operation during computation. These findings establish the first demonstration of an unmodified 6T SRAM-based reconfigurable CAM with integrated similarity-index capability, highlighting its potential as a versatile and energy-efficient IMC solution for next-generation AI and low-power edge applications.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"188-202"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148513552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Energy-Efficient Epileptic Seizure Prediction Using RRAM-Based In-Memory Computing","authors":"Ahmedul Khan;Shiva Maleki Varnosfaderani;Mohammad Alhawari;Gozde Tutuncuoglu","doi":"10.1109/JETCAS.2026.3668819","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3668819","url":null,"abstract":"This work investigates the feasibility of an energy-efficient resistive random-access memory (RRAM) crossbar array framework for epileptic seizure prediction using the CHB-MIT electroencephalogram (EEG) dataset. Traditional von Neumann architectures face limitations in scalability and energy efficiency for real-time medical applications, motivating the exploration of in-memory computing with RRAM devices. We develop a domain-specific feature extraction methodology tailored to EEG signals and implement a seizure prediction algorithm that can be mapped directly onto a crossbar-based architecture. To evaluate the robustness of the approach, the extracted features were quantized to a 1-bit representation and processed as inputs. Despite the aggressive quantization, the proposed workflow achieved mean prediction accuracies exceeding 75% for hardware inference, demonstrating resilience to reduced precision. Furthermore, the system exhibits extremely low read energy consumption at the picojoule level, enabling performance metrics far surpassing conventional digital platforms. The combination of high accuracy, ultra-low power requirements, and hardware-friendly implementation highlights the promise of RRAM-based in-memory computing as a scalable solution for real-time, patient-specific epilepsy monitoring and intervention in wearable and implantable devices.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"538-548"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148433315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"TetrisG-SDK: Efficient Convolutional Layer Mapping With Adaptive Windows and Grouped Convolutions for Fast In-Memory Computing","authors":"Ke Dong;Kejie Huang;Tao Luo;Bo Wang","doi":"10.1109/JETCAS.2026.3689154","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3689154","url":null,"abstract":"Shifted-and-Duplicated-Kernel (SDK) mapping has emerged as an effective strategy to accelerate convolutional layers on compute-in-memory (CIM) hardware. However, existing SDK variants (e.g., VWC-SDK) merely optimize mapping for a single CIM macro, leaving inter-macro parallelism unexplored. Moreover, their mapping methodologies are still suboptimal. To address these limitations, we present TetrisG-SDK, a novel framework that employs adaptive windows to boost mapping performance. The proposed windows accommodate more input channels, increase array utilization at marginal space, and adapt to different channel depths. More importantly, TetrisG-SDK reduces compute latency by searching for optimal window configurations across multiple CIM macros with a fixed hardware budget. Besides, it incorporates grouped convolution to further decrease computing cycles while maintaining near-lossless model accuracy. In addition, TetrisG-SDK integrates a validated CIM hardware simulator to provide accurate system-/application-level estimations of latency, area and energy. Compared to the single-macro VWC-SDK, the proposed framework achieves a speed-up by <inline-formula> <tex-math>$1.2times $ </tex-math></inline-formula>, <inline-formula> <tex-math>$1.3times $ </tex-math></inline-formula>, and <inline-formula> <tex-math>$1.3times $ </tex-math></inline-formula> for CNN8, GoogLeNet Inception, and DenseNet40 models, respectively. When deployed on the simulator, it reduces system-level latency and energy by <inline-formula> <tex-math>$2.4times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$1.7times $ </tex-math></inline-formula> for CNN8, <inline-formula> <tex-math>$1.3times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$1.2times $ </tex-math></inline-formula> for Inception, and <inline-formula> <tex-math>$1.3times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$1.6times $ </tex-math></inline-formula> for DenseNet40, respectively. When leveraging macro-level parallelism, TetrisG-SDK reduces the <italic>Energy-Delay-Area-Product (EDAP)</i> by 70% for CNN8, 68% for Inception, and 36% for DenseNet40 compared to its non-grouped counterpart. These results manifest that TetrisG-SDK is a promising solution to efficiently mapping convolutional layers on CIM hardware.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"363-377"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148514480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"In-Sensor RRAM Architecture for Vision Processing at the Edge","authors":"Pantelis Fraidakis;Emmanouil Stavroulakis;Evangelos Tsipas;Alexandros-Eleftherios Mavropoulis;Iosif-Angelos Fyrigos;Panagiotis Dimitrakis;Georgios Ch. Sirakoulis","doi":"10.1109/JETCAS.2026.3668174","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3668174","url":null,"abstract":"To address the latency and energy bottlenecks caused by the physical separation of sensing and processing in conventional vision systems, we propose a novel in-sensor, in-memory architecture based on a fabricated monolithic 1D1R stack. The unit cell comprises a photodiode in series with a resistive random-access memory (RRAM) device, enabling computation at the point of capture. Organized into complementary crossbar arrays and driven by programmable peripheral units, this architecture supports image acquisition, temporal-difference motion extraction, spatial filtering, box blur filtering, and morphological dilation directly within the sensor plane. System-level transient simulations using validated device models demonstrate the system’s robustness against non-idealities and its capability for dynamic exposure control via multi-state programming. Large-scale performance analyses validate the architecture’s efficiency, confirming that processing latency scales linearly with image height, independent of the width, across all operating modes. This capability yields processing speeds of approximately 336 frames per second for motion extraction and box-blur filtering. Furthermore, the system demonstrates energy consumption as low as 1.89 nJ per pixel for temporal differencing and 2.43 nJ per pixel for image capture. In-memory spatial filtering (box-blur) is achieved with high structural fidelity (SSIM >0.97) at 3.13 nJ per pixel, while higher-level morphological dilation is executed at 3.22 nJ per pixel. Collectively, these performance metrics establish the proposed architecture as a versatile, reconfigurable, high-speed platform optimized for edge vision applications.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"427-440"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11411779","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148433344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Time-Based 8TD SRAM CIM Macro With Low PVT Sensitivity for Edge Devices","authors":"Andrea Fasolino;Pio Esposito;Rosalba Liguori;Luigi Di Benedetto;Alfredo Rubino;Gian Domenico Licciardo","doi":"10.1109/JETCAS.2026.3691668","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3691668","url":null,"abstract":"Computing-in-Memory (CIM) promises to overcome the von Neumann bottleneck; however, analog CIM designs face challenges such as read disturbance, nonlinearity, and process-voltage-temperature (PVT) variations. Therefore, this paper presents an 8-transistor SRAM CIM macro with built-in PVT robustness to tackle these challenges. The proposed dynamic cascode SRAM bitcell utilizes stacked high- and low-Vth NMOS access devices and multilevel current-mode word-line driving to enhance read stability and achieve up to 54-fold lower bitcell current variability without requiring separate read/write ports. A subthreshold current-starved ring oscillator and a transmission-gate counter perform time-based analog-to-digital conversion of MAC results, achieving an integral nonlinearity of <0.5>2</sup> and an area efficiency of 31.32 TOPS/mm² for 2-bit inputs and 1-bit weights. The <inline-formula> <tex-math>$64times 128$ </tex-math></inline-formula> macro maintains functionality from 0.65 V to 1.2 V and yields <0.8% MNIST accuracy loss, demonstrating robust, energy-efficient CIM for edge AI.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"252-261"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11513495","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148513313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Performance Investigation of HfOX-Based 1-Transistor–1-Memristor Cell for In-Memory Logic Gates Implementation","authors":"Mani Shankar Yadav;Sukesh Gupta;Avinash Kumar Gupta;Brajesh Rawat","doi":"10.1109/JETCAS.2026.3683734","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3683734","url":null,"abstract":"The transistor–memristor (1T-1M) integration has been recognized as an effective strategy to suppress crosstalk between neighboring cells for the development of a practical crossbar architecture, though its adoption for in-memory Boolean logic gate implementation is still missing. In this regard, we systematically investigate HfO_X-based 1T-1M cell for in-memory logic gates implementation employing the Memristor-Aided loGIC (MAGIC) design style. This performance analysis is carried out using a fully calibrated and physics-based Stanford-PKU model, which captures full I–V switching dynamics, including temperature and stochastic effects. Our results show that the 1T-1M cell with the Gate and Source-controlled Off-State RESET (GSOSR) scheme substantially increases the high resistance state (HRS), which enables nearly <inline-formula> <tex-math>$2.2times $ </tex-math></inline-formula> higher on-off resistance ratio compared to the 1M cell and achieves significant energy saving in execution operation for AND, NAND, XOR, and XNOR gates. Despite the 1T-1M cell exhibiting a slight increase in delay due to additional capacitances, the associated energy reduction and improved reliability outweigh this penalty. Variability analysis further reveals that the XOR gate with 1T-1M cell suppresses resistance fluctuation in both low resistance state (LRS) and HRS by up to <inline-formula> <tex-math>$3times $ </tex-math></inline-formula> under worst-case corners, which ensures more robust operation over 1M cell. Overall, our findings demonstrate that the 1T-1M cell offers a viable path toward a scalable, energy-efficient, robust, and crossbar-compatible in-memory computing system, surpassing the widely employed 1M cell architecture.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"169-179"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148513322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ShiftMUX: Reconfigurable 4:1 MUX-Based In-Memory Shifter for Multiplication-Less Deep Neural Network Accelerations","authors":"Vinodh Kumar Bose;Rajiv V. Joshi;Yu Cao;Binsu J. Kailath","doi":"10.1109/JETCAS.2025.3649741","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3649741","url":null,"abstract":"This paper presents <italic>ShiftMUX</i>, a reconfigurable 4:1 multiplexer (MUX)-based in-memory computing (IMC) architecture for multiplier-less deep neural network (DNN) acceleration. The proposed design completes its operation in only three cycles, compared with at least ten cycles in prior approaches. Beyond basic logic, ShiftMUX supports complex functions such as full adder, full subtractor, and comparator, eliminating the need for separate mapping and control peripherals. When cascaded in a crossbar, multiple MUX units realize <inline-formula> <tex-math>$N$ </tex-math></inline-formula>-bit shift operations including logical, arithmetic, circular, and universal shifts enabling efficient power-of-two multiplications for quantized DNNs. Circuit-level simulations in 45 nm technology show write energy of 32 pJ, read delay of 9.14 ps, and a total energy consumption of 240 pJ for a 4-bit multiplier, outperforming state-of-the-art designs. A Vision Transformer model exhibits only a + 2.66% accuracy deviation with shift-based multiplication, confirming the suitability of ShiftMUX for modern AI models. Moreover, the architecture reduces computation overhead by more than 90%, requiring only <inline-formula> <tex-math>$N + log _{2}(N) + 2$ </tex-math></inline-formula> cycles, and achieves up to <inline-formula> <tex-math>$9times $ </tex-math></inline-formula> speedup in multiplication. ShiftMUX thus provides a scalable, reconfigurable, and energy-efficient solution for low-latency DNN acceleration in edge and high-performance computing systems.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"327-337"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148513796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Universal Multistable Memristor Feedback Scheme for Designing Multi-Scroll/Wing Chaotic Systems Without Equilibria","authors":"Zhijun Li;Luyao Tong;Chunlai Li","doi":"10.1109/JETCAS.2025.3638254","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3638254","url":null,"abstract":"In recent years, chaotic systems featuring multi-scroll/wing structures with hidden dynamics have garnered growing interest. Existing design methods, however, are often tailored to specific systems and lack generality. To address this limitation, this paper proposes a universal multistable memristor feedback scheme (MMFS) for constructing multi-scroll/wing chaotic systems devoid of equilibria. The scheme integrates an equilibrium-free seed system with a memristive feedback network and a state feedback controller. Mechanism analysis reveals that the multi-scroll/wing structures originate from virtual equilibria mapped from the stable fixed points of the memristors. The scheme’s generality and effectiveness are verified through three distinct chaotic systems: a double-scroll system, a double-wing system, and a conservative chaotic system. Numerical simulations and DSP-based hardware experiments show close agreement. Furthermore, the number of scrolls/wings can be precisely controlled by adjusting memristor parameters. As a practical application, a pseudo-random number generator based on a multi-wing system is implemented, showcasing its potential for cryptographic applications.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"629-640"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148433225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"EFFP-NMC: An Energy-Efficient and Flexible Floating-Point Framework for Near-MRAM Computing","authors":"Chi-An Liao;Tsung-Te Liu","doi":"10.1109/JETCAS.2026.3668015","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3668015","url":null,"abstract":"Deep neural networks increasingly rely on floating-point (FP) formats to preserve accuracy and stability, but their integration with near-memory computing (NMC) faces significant energy efficiency challenges. MRAM offers low standby power and non-volatility for edge AI, yet suffers from high read-access energy, while FP workflows introduce costly alignment overhead. This work presents a flexible MRAM-based FP-NMC macro with three complementary innovations. Kernel-Wise Word-Line Mapping (KW-WLM) lowers access-activation complexity from <inline-formula> <tex-math>$O(N^{2})$ </tex-math></inline-formula> to <inline-formula> <tex-math>$O(N)$ </tex-math></inline-formula>, achieving <inline-formula> <tex-math>$10.1-2041times $ </tex-math></inline-formula> energy efficiency gain based on the image resolution, by maximizing weight reuse across pixels. Moreover, Delta-Exponent Aware Read (DEAR) introduces a lightweight control scheme that dynamically adjusts read granularity to exponent values, cutting redundant fetches and achieving <inline-formula> <tex-math>$1.22-1.77times $ </tex-math></inline-formula> energy reduction. Finally, Multiple Reconfigurable Computing Schemes (MRCS) enable layer-wise precision reconfiguration, providing up to <inline-formula> <tex-math>$1.14times $ </tex-math></inline-formula> energy efficiency gains while retaining near-software accuracy. These innovations mitigate MRAM’s access-energy bottlenecks and FP alignment overhead, enabling scalable, precision-flexible inference for real-world AI deployment.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"514-524"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148433269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}