IEEE Journal on Emerging and Selected Topics in Circuits and Systems最新文献

{"title":"Fast and Accurate Jitter Amplification Modeling With Variable Pulse Width Response for Statistical BER Analysis in Chiplet Interconnects and Beyond","authors":"Shenggao Li;Maher Amer","doi":"10.1109/JETCAS.2025.3592902","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3592902","url":null,"abstract":"In this paper, we investigate Statistical Bit Error Rate (BER) analysis for low-loss short-reach chiplet interface and high-loss long-reach serial interface. We used jitter filtering to account for the residue jitter not tracked by a forwarded clock system and proposed a fast and exact Statistical BER method to account for the Tx jitter amplification effect in a high-loss channel. Our proposed method achieves a linear computation complexity.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 4","pages":"609-618"},"PeriodicalIF":3.8,"publicationDate":"2025-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11097288","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145808574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Democratizing Customization for ML at the Edge Through Hetero-Chiplet SiP Architectures","authors":"Matthew Joseph Adiletta;Gu-Yeon Wei;David Brooks","doi":"10.1109/JETCAS.2025.3592677","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3592677","url":null,"abstract":"The demand for efficient machine learning in edge devices is challenging the capabilities of general-purpose computing systems. While domain-specific System on Chip (SoCs) are efficient, they are often prohibitively expensive due to long design times and high design costs. To address these limitations, the community has begun to explore System in Package (SiP) designs for low-cost assembly of reusable accelerators, available as chiplets, to democratize customization. This presents a new challenge of <italic>macro-architecture</i> design space exploration (DSE). Prior works do not address this problem, having only investigated micro-architecture design and optimization of homogeneous SiPs. To address this need, and unlock the potential of assembling custom SiPs, comprising heterogeneous chiplets, we introduce an early DSE framework, <italic>CASCADE</i> – A. <italic>CASCADE</i> employs fast, first-order performance models to capture the tradeoffs of composable compute chiplets, leveraging tool-generated traces to comprehend dataflow patterns in the context of state-of-the-art machine learning tasks. Using <italic>CASCADE</i>, we assess the performance benefits of composable SiPs comprising hetero-chiplets for single-tenant and two-tenant scenarios. Notably, we demonstrate that hetero-chiplet systems can deliver speedups in the range of 3-5x, depending on the application, compared to a baseline GPU chiplet system.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 4","pages":"634-647"},"PeriodicalIF":3.8,"publicationDate":"2025-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11096615","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145808635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Extending Energy-Efficient and Scalable DNN Training and Inference With 3-D Photonic Accelerator","authors":"Juliana Curry;Yuan Li;Ahmed Louri;Avinash Karanth;Razvan Bunescu","doi":"10.1109/JETCAS.2025.3591812","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3591812","url":null,"abstract":"As deep neural network (DNN) models continue to grow in complexity, analog computing architectures have emerged as a promising solution to meet increasing computational demands. Among these, silicon photonic computing excels at efficiently executing dot product operations while leveraging inherent parallelism. Photonic phase change memory (photonic-PCM) further enhances photonic computing by enabling scalable, non-volatile storage. In this work, we introduce the 3D Large-Scale Photonic Accelerator (LSPA), a novel photonic computing architecture designed for large-scale DNN models. LSPA employs multi-layered 3D stacking of non-volatile photonic-PCM cells, creating a high-density computational fabric that optimizes energy efficiency, flexibility, and scalability. LSPA’s custom 3D photonic network enables simultaneous data multicast in two dimensions and accumulation in three dimensions, optimizing communication patterns essential for efficient DNN training. A distinctive feature of LSPA is its ability to execute multiple forward and backward passes in parallel within each mini-batch, reducing latency associated with data movement and photonic-PCM programming. This unique capability combined with high-bandwidth photonic interconnects allows LSPA to sustain efficient training across a wide range of DNN workloads. When evaluated against a range of neural network models including VGG-16, ResNet-50, GoogLeNet, Transformer, GNMT, LLaMA 7B, and LLaMA 30B, LSPA reduces execution time by up to 92% and energy consumption by up to 90%. These results highlight LSPA as a transformative advancement in scalable, high-performance photonic computing for deep learning.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 4","pages":"560-576"},"PeriodicalIF":3.8,"publicationDate":"2025-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145808592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Through Silicon Via (TSV) Architecture of the Bumpless Build Cube (BBCube) for Stacked Memory Devices","authors":"Shinji Sugatani;Hiroyuki Ryoson;Norio Chujo;Masao Taguchi;Koji Sakui;Takayuki Ohba","doi":"10.1109/JETCAS.2025.3591627","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3591627","url":null,"abstract":"This paper describes the architecture of the wafer-on-wafer (WOW) via-last through silicon via (TSV), named Bumpless Build Cube-TSV (BBCube-TSV). At first, the three types of TSVs, <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>-bump technology, hybrid bonding technology, and BBCube-TSV are overviewed, addressing the detailed structures and the opportunities of applying for 3D-memories. Then, the process steps of the BBCube-TSV are summarized to figure out the key process steps. Three types of applications are reviewed to illustrate and discuss the potentiality of the BBCube-TSV to enhance 3D-memories, power delivery wiring in processor on stacked memory devices, and advantage in defect management with sophisticated ideas on stacked memories. The simplicity of the structure and the occupation of copper in the TSV structure are found to provide the advantages. The role of the TSV as a vertical interconnect in the hierarchy of multilayer wiring is discussed.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 3","pages":"368-378"},"PeriodicalIF":3.8,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11088080","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145059835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Iterative Layout-Aware Power, Thermal, and IR-Drop Co-Optimization: Ensuring Convergency in 3D-ICs","authors":"Mohamed Naeim;Dwaipayan Biswas;Yun Dai;Odysseas Zografos;Herman Oprins;Geert Van der Plas;C. T. Kao;Pinhong Chen;Dragomir Milojevic","doi":"10.1109/JETCAS.2025.3591727","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3591727","url":null,"abstract":"Continuous scaling of integrated circuits and the adoption of 3D integration have significantly increased power density, creating critical challenges for thermal and power integrity. Rising power densities can trigger thermal runaway, negatively impacting device reliability and performance. This paper presents an electrothermal coupling framework built upon commercial Electronic Design Automation (EDA) tools, designed for precise iterative analysis of power, thermal and IR-drop characteristics in 2D and 3D configurations of a many-core RISCV SoC. The proposed framework automates iterative Power-Temperature (P-T) simulations to evaluate thermal convergence and potential thermal runaway scenarios in Memory-on-Logic (MoL) and Logic-on-Memory (LoM) stacked configurations. It identifies thermal hotspots, tracks their progression and evaluates various cooling strategies. Initial results indicate that the first P-T iteration provides up to 10% power savings in 3D due to a 11% wirelength reduction compared to 2D. However, by the fifth iteration, MoL power saving reduces to 4%, whereas LoM maintains the 10% saving. LoM exhibits a 6°C lower peak temperature compared to MoL under equivalent cooling conditions. Compared to 2D, the range of power densities (110 - <inline-formula> <tex-math>$260~W/cm^{2}$ </tex-math></inline-formula>) results in temperature variations of <inline-formula> <tex-math>$-1^{circ } C$ </tex-math></inline-formula> to <inline-formula> <tex-math>$+3^{circ } C$ </tex-math></inline-formula> in LoM. A <inline-formula> <tex-math>$10^{circ } C$ </tex-math></inline-formula> rise in temperature increases IR-drop by 11%; however, physical design-aware adjustments, such as a tighter Power Delivery Network (PDN) pitch, effectively reducing IR-drop by 54%, mitigating thermal impacts.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 4","pages":"648-658"},"PeriodicalIF":3.8,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145808618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Bumpless Build Cube (BBCube) 3D: Heterogeneous 3D Integration Using WOW and COW","authors":"Norio Chujo;Hiroyuki Ryoson;Koji Sakui;Shinji Sugatani;Masao Taguchi;Takayuki Ohba","doi":"10.1109/JETCAS.2025.3591677","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3591677","url":null,"abstract":"We propose a novel technology called Bumpless Build Cube (BBCubeTM) 3D for AI and high-performance computing (HPC) applications that require high bandwidth and power efficiency. BBCube 3D is constructed through heterogeneous 3D integration, in which xPU (e.g., CPU, GPU, TPU) chiplets and DRAM dies are stacked using a combination of bumpless wafer-on-wafer (WoW) and chip-on-wafer (CoW) processes. The bumpless stacking process adopts a method similar to multilevel metallization in the back-end-of-line (BEOL), enabling BBCube to provide reliable and high-density interconnects between dies. Moreover, BBCube features low-capacitance and low-impedance through-silicon vias (TSVs) due to the use of thin silicon and slim TSV structures. To further enhance performance, a highly parallel DRAM architecture leveraging the bumpless WoW process is introduced. The high-density TSVs enable lower data transmission speeds without compromising bandwidth. Additionally, the adoption of four-phase shielded I/Os (FPS-I/O) allows for a reduction in power supply voltage. BBCube 3D has the potential to achieve a bandwidth 30 times higher than DDR5 and four times higher than HBM2E, while achieving bit access energy consumption reduced to one-twentieth that of DDR5 and one-fifth that of HBM2E. The low-impedance TSVs in BBCube ensure robust power integrity for the xPU stacked on top of the layered DRAM. Furthermore, integrating an xPU on top of the Cube enables efficient cooling of high-power xPUs. BBCube can accommodate an xPU with a power density exceeding 50 W/cm² — comparable to the latest GPUs — while maintaining the DRAM temperature below 95°C.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 3","pages":"404-414"},"PeriodicalIF":3.8,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145061955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient Die-to-Die Communication: UCIe Link Simulation and Optimization in a Chiplet-Based System","authors":"Kunyue Li;Shuaipeng Li;Xiaoyan Li;Zizheng Dong;Sai Gao;Jialei Sun;Naifeng Jing;Qin Wang;Guanghui He;Jianfei Jiang","doi":"10.1109/JETCAS.2025.3590822","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3590822","url":null,"abstract":"With the increasing complexity of chiplet-based architectures and the growing adoption of heterogeneous computing, efficient and high-precision simulation frameworks are essential for evaluating chiplet interconnect performance. This paper presents an implementation of the UCIe protocol (Universal Chiplet Interconnect Express) within the gem5 simulation environment, providing a comprehensive system-level modeling framework for UCIe-based interconnects. The proposed UCIe link model supports full-stack protocol simulation, including transaction-level processing, die-to-die adaptation, and physical layer interactions. A flit-based packing mechanism is introduced to enable accurate transmission modeling, and an Ack/Nak-based retry mechanism is introduced to ensure robust data integrity. An optimized event-driven scheduling strategy is incorporated to address performance bottlenecks observed in traditional UCIe simulations. Experimental evaluations validate the accuracy and efficiency of the proposed UCIe link model by comparing its latency with theoretical values under different computational workloads. The results show that the model closely matches the theoretical predictions, with a latency deviation of less than 0.5% in most cases. Additionally, performance comparisons between UCIe interconnect, PCIe interconnect, and direct memory transfer reveal that UCIe incurs only a minor protocol overhead (less than 0.7%), making it a practical and scalable solution for multi-chipset interconnects. The proposed UCIe simulation framework provides a high-precision virtual verification platform for chiplet system design, enabling low-cost, high-accuracy performance evaluations, and lays the foundation for future optimizations in large-scale chiplet-based architectures.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 4","pages":"599-608"},"PeriodicalIF":3.8,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145808569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Implementation of Delay Testable Boundary Scan and Post-Bond Test Results in a 3D IC","authors":"Hiroyuki Yotsuyanagi;Keigo Takami;Masaki Hashizume","doi":"10.1109/JETCAS.2025.3591617","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3591617","url":null,"abstract":"A defective through-silicon via (TSV) may cause a small delay fault that is difficult to detect using conventional logic testing methods. Testing TSVs used for chip-to-chip interconnection in 3D stacked ICs is a challenging problem. We have proposed a delay testable boundary scan design that has an embedded time-to-digital converter that can measure the timing slack between the test clock and an incoming signal through a TSV. A prototype 3D stacked IC with this delay testable circuit was fabricated using TSVs of various diameters. The measurement results show that the proposed delay testable boundary scan can effectively identify both logic errors that occurred in TSVs with open defects due to a small diameter and outliers in delay through a TSV that have no logic errors.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 3","pages":"469-477"},"PeriodicalIF":3.8,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145061965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Chiplets Interface Protocol (ChIP) for Ultra-Large-Scale Applications","authors":"Arvin Delavari;Boris Vaisband","doi":"10.1109/JETCAS.2025.3591559","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3591559","url":null,"abstract":"As computational workloads continue to grow, heterogeneous integration of chiplet-based systems is becoming critically important for data-intensive applications such as high-performance computing, large language models, and artificial intelligence. Scaling to ultra-large-scale (ULS) systems introduces, however, significant communication challenges due to the limitations of network architectures and packaging technologies. Efficient data transfer across a network of thousands of chiplets remains a critical bottleneck. A robust, low-latency, area- and energy-efficient communication architecture for ULS system named Chiplet Interface Protocol (ChIP) is proposed in this work. ChIP supports burst transfers and out-of-order transactions while leveraging the simple universal parallel interface for chips (SuperCHIPS)—a simple area- and energy-efficient streaming channel at the physical layer. Evaluated on a wafer-scale platform, ChIP was compared to state-of-the-art (SOTA) chiplet-based interfaces, including LIPINCON, BoW, UCIe, and AIB, in performance, hardware efficiency, and unified signaling figures of merit. From the comparison results, ChIP significantly outperforms the SOTA alternatives (<inline-formula> <tex-math>$5.53times $ </tex-math></inline-formula> better) in bandwidth per shoreline, reaching 2.2 Tbps/mm in pipelined mode and up to 7.3 Tbps/mm in burst transactions. In addition, the transceiver area per link in ChIP is <inline-formula> <tex-math>$485~mu $ </tex-math></inline-formula>m²—46.1% smaller than the best SOTA alternative—while achieving 0.38–0.53 pJ/bit energy and 1 ns latency in 45 nm CMOS over a 0.5 mm link, with efficiency sustained across longer channels and varied packaging due to minimal handshaking and optimized point-to-point specifications. The performance of ChIP is evaluated across multiple network configurations on a fine-pitch integration platform, and also for a customized hybrid topology, referred to as the network on interconnect fabric (NoIF), that is introduced and analyzed in this work. The architecture of the NoIF forms the foundation for ULS computing platforms, delivering exceptional results as compared to SOTA solutions. The superior hardware efficiency and advanced inter-chiplet communication features of ChIP position this proposed protocol as an ideal candidate for chiplet communication in ULS architectures.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 4","pages":"585-598"},"PeriodicalIF":3.8,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11088081","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145808602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal Perspective Design and Analysis of Multi-Stacked Structures","authors":"Tianjian Liu;Jie Wu;Zhen Chen;Shujuan Liu;Zhongkai Jiang;Haoyang Peng;Zhandi Yang;Xing Hu;Dong Xie;Fang Dong;Yiqun Wang;Sheng Liu","doi":"10.1109/JETCAS.2025.3590877","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3590877","url":null,"abstract":"This paper investigates the thermal performance of multi-layer metal interconnects in three-dimensional (3D) stacked structures through finite element analysis (FEA). The 3D integrated circuit (3D IC) consists of five vertically stacked chips. The interconnections between the chips are achieved through through-silicon vias (TSVs), metal redistribution layers (RDLs), and hybrid bonding. Due to the complexity of the 3D IC structure, this work simplifies the detailed 3D IC model by employing equivalent models for each chip layer and the hybrid bonding structure. The study reveals that the portion of Cu significantly affects the thermal conductivity of the hybrid bonding structure, exhibiting quasi-linear dependence. Additionally, the misalignment between the upper and lower Cu pads decreases the thermal conductivity of the structure. Furthermore, equivalent models for different chip layers, including metal interconnect layers and TSVs, are constructed based on specific cases, and the equivalent thermal conductivities are extracted accordingly. Based on the equivalent results of each layer, the thermal conductivity of the complex 3D IC structure is ultimately determined. This work provides valuable results and guidance for the thermal design and practice of 3D IC.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 3","pages":"438-444"},"PeriodicalIF":3.8,"publicationDate":"2025-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145061852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}