IEEE Journal on Emerging and Selected Topics in Circuits and Systems最新文献_第9页

Low-Loss and Compact Millimeter-Wave Silicon-Based Filters: Overview, New Developments in Silicon-on-Insulator Technology, and Future Trends 低损耗和紧凑型毫米波硅基滤波器：概览、绝缘体上硅技术的新发展和未来趋势

IF 4.6 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2023-12-21 DOI: 10.1109/JETCAS.2023.3345476

Robert Nericua;Ke Wang;He Zhu;Roberto Gómez-García;Xi Zhu

{"title":"Low-Loss and Compact Millimeter-Wave Silicon-Based Filters: Overview, New Developments in Silicon-on-Insulator Technology, and Future Trends","authors":"Robert Nericua;Ke Wang;He Zhu;Roberto Gómez-García;Xi Zhu","doi":"10.1109/JETCAS.2023.3345476","DOIUrl":"https://doi.org/10.1109/JETCAS.2023.3345476","url":null,"abstract":"This paper presents an overview of Silicon-based millimeter-wave (mm-wave) passive devices for bandpass and bandstop filtering applications, while also reporting originally-conceived filter developments and future trends. First of all, the state-of-the-art on mm-wave low-loss bandpass filters (BPFs) is covered, and new BPF designs are shown. The engineered BPFs employ a center-tapped ring architecture with shunt-connected capacitors to realize a standard 2nd-order baseline BPF design, which is subsequently scaled to 30-GHz and 60-GHz operational frequencies. To increase the selectivity as well as the stopband rejection levels of this baseline BPF, the in-series cascade connection of the baseline BPF units is used for a higher-order BPF realization. For experimental-validation purposes, a total of four mm-wave BPFs based on these design strategies are implemented, fabricated in 45-nm Silicon-on-Insulator (SOI) complementary-metal-oxide-semiconductor-(CMOS) technology, and tested. Afterward, a review of Silicon-based-integrated bandstop filters (BSFs) operating in the mm-wave region is provided, which includes both reflective-type and reflectionless/absorptive filter realizations for RF-interference-suppression in highly-congested electromagnetic (EM) environments. Finally, future research trends in the Silicon-based-integrated filter area are discussed. They are expected to play a key role in the development of modern radio-frequency (RF) front-ends for emerging beyond 5G and EM-sensing scenarios.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"14 1","pages":"30-40"},"PeriodicalIF":4.6,"publicationDate":"2023-12-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140123558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 340-GHz THz Amplifier-Frequency-Multiplier Chain With 360° Phase-Shifting Range and its Phase Characterization 具有 360° 相移范围的 340 GHz 太赫兹放大器-频率-倍增器链及其相位特性分析

IF 4.6 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2023-12-21 DOI: 10.1109/JETCAS.2023.3345358

Chun Wang;Pin-Chun Chiu;Chun-Lin Ko;Sheng-Hsiang Tseng;Chun-Hsing Li

{"title":"A 340-GHz THz Amplifier-Frequency-Multiplier Chain With 360° Phase-Shifting Range and its Phase Characterization","authors":"Chun Wang;Pin-Chun Chiu;Chun-Lin Ko;Sheng-Hsiang Tseng;Chun-Hsing Li","doi":"10.1109/JETCAS.2023.3345358","DOIUrl":"https://doi.org/10.1109/JETCAS.2023.3345358","url":null,"abstract":"A 340-GHz compact terahertz (THz) amplifier-frequency-multiplier chain (AMC) offering a full 360° phase shifting range for phased-array applications is proposed in this paper. The AMC comprises an 85 -GHz phase-shifter-embedded (\u0000<inline-formula> <tex-math>$Delta varphi $ </tex-math></inline-formula>\u0000-embedded) power amplifier (PA) and a high-output-power frequency quadrupler (FQ). The PA is equipped with multifunctional impedance matching networks (M-IMNs) that can simultaneously provide balun, impedance transformation, and phase-shifting functions. Analytic expressions have been derived to provide design guidelines for the M-IMNs. With the integrated M-IMNs, the proposed PA can concurrently deliver high output power and a phase shift exceeding 90° in a compact chip area. The proposed FQ can achieve optimal impedance matching at second and fourth harmonic frequencies, leading to the output power enhancement of 2.6 dB. Furthermore, the output phase of the PA is quadrupled by the FQ, resulting in the output signal of the AMC with a full 360° phase-shifting capability. A measurement setup for characterizing the phase of a THz signal is also presented. Implemented in a 40-nm CMOS technology without ultra-thick metal layers available, the proposed THz AMC achieves a peak output power of −3.5 dBm at 368 GHz with a conversion gain of 1.8 dB and a 3-dB bandwidth from 340 to 376 GHz. The output phase can continuously vary over 360° within the 324 to 346 GHz frequency range. The phase noise of the output signal at 346 GHz is −105 dBc/Hz at a 10-MHz offset frequency. The proposed 340-GHz AMC consumes 215.1 mW from a 0.9-V supply.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"14 1","pages":"52-66"},"PeriodicalIF":4.6,"publicationDate":"2023-12-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140123406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 11.3–16.6-GHz VCO With Constructive Switched Magnetic Coupling in 65-nm CMOS 采用 65 纳米 CMOS 的 11.3-16.6-GHz VCO，具有构造性开关磁耦合功能

IF 4.6 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2023-12-18 DOI: 10.1109/JETCAS.2023.3344510

Yuetong Lyu;Changwenquan Song;Pei Qin;Liang Wu

{"title":"A 11.3–16.6-GHz VCO With Constructive Switched Magnetic Coupling in 65-nm CMOS","authors":"Yuetong Lyu;Changwenquan Song;Pei Qin;Liang Wu","doi":"10.1109/JETCAS.2023.3344510","DOIUrl":"https://doi.org/10.1109/JETCAS.2023.3344510","url":null,"abstract":"Conventional transformer-based magnetic tuning has demonstrated dual-band or even multi-band operation for voltage-controlled oscillators (VCOs). However, the destructive magnetic coupling employed introduces implicit loss to the transformer thus degrading its quality factor (Q), and achieves a continuous frequency coverage resulting in inferior performance. To address this issue, this paper proposes a constructive switched magnetic coupling (CSMC) technique, realizing dual-band operation with the Q improvement into one band due to the in-phase coupling and the explicit switch. For validation, a transformer employing the CSMC technique is designed and deployed in a dual-band VCO design. Fabricated in a 65-nm CMOS process, the VCO is measured with an oscillation frequency range of 37.8%, from 11.3 to 16.6 GHz, while consuming 2.5-mW from a 0.65-V voltage supply. Within the entire frequency coverage, the measured phase noise ranges from −129.6 to −123.7 at 10-MHz offset, resulting in FoM of 186-192.1 dBc/Hz. The core area of the chip is \u0000<inline-formula> <tex-math>$0.43times 0.25$ </tex-math></inline-formula>\u0000 mm2 excluding pads.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"14 1","pages":"133-141"},"PeriodicalIF":4.6,"publicationDate":"2023-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140123365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Compact Transverse-Resonance Low-Pass Filter With Wide Stop-Band Rejection Implemented in Gallium Arsenide Technology 利用砷化镓技术实现具有宽带抑制功能的紧凑型横向谐振低通滤波器

IF 4.6 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2023-12-07 DOI: 10.1109/JETCAS.2023.3340957

Sudipta Chakraborty;Gayatri Neeharika Sreepada;Michael Heimlich;Anand K. Verma

引用次数: 0

Building Time-Surfaces by Exploiting the Complex Volatility of an ECRAM Memristor 利用 ECRAM Memristor 的复杂波动性构建时间曲面

IF 4.6 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2023-11-16 DOI: 10.1109/JETCAS.2023.3330832

Marco Rasetto;Qingzhou Wan;Himanshu Akolkar;Feng Xiong;Bertram Shi;Ryad Benosman

{"title":"Building Time-Surfaces by Exploiting the Complex Volatility of an ECRAM Memristor","authors":"Marco Rasetto;Qingzhou Wan;Himanshu Akolkar;Feng Xiong;Bertram Shi;Ryad Benosman","doi":"10.1109/JETCAS.2023.3330832","DOIUrl":"https://doi.org/10.1109/JETCAS.2023.3330832","url":null,"abstract":"Memristors have emerged as a promising technology for efficient neuromorphic architectures owing to their ability to act as programmable synapses, combining processing and memory into a single device. Although they are most commonly used for static encoding of synaptic weights, recent work has begun to investigate the use of their dynamical properties, such as Short Term Plasticity (STP), to integrate events over time in event-based architectures. However, we are still far from completely understanding the range of possible behaviors and how they might be exploited in neuromorphic computation. This work focuses on a newly developed Li\u0000<inline-formula> <tex-math>$_{text {x}}$ </tex-math></inline-formula>\u0000WO\u0000<inline-formula> <tex-math>$_{text {3}}$ </tex-math></inline-formula>\u0000-based three-terminal memristor that exhibits tunable STP and a conductance response modeled by a double exponential decay. We derive a stochastic model of the device from experimental data and investigate how device stochasticity, STP, and the double exponential decay affect accuracy in a hierarchy of time-surfaces (HOTS) architecture. We found that the device’s stochasticity does not affect accuracy, that STP can reduce the effect of salt and pepper noise in signals from event-based sensors, and that the double exponential decay improves accuracy by integrating temporal information over multiple time scales. Our approach can be generalized to study other memristive devices to build a better understanding of how control over temporal dynamics can enable neuromorphic engineers to fine-tune devices and architectures to fit their problems at hand.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"13 4","pages":"877-888"},"PeriodicalIF":4.6,"publicationDate":"2023-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10320285","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139060149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low-Area and Low-Power VLSI Architectures for Long Short-Term Memory Networks 短时长内存网络的低面积、低功耗 VLSI 架构

IF 4.6 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2023-11-06 DOI: 10.1109/JETCAS.2023.3330428

Mohammed A. Alhartomi;Mohd Tasleem Khan;Saeed Alzahrani;Ahmed Alzahmi;Rafi Ahamed Shaik;Jinti Hazarika;Ruwaybih Alsulami;Abdulaziz Alotaibi;Meshal Al-Harthi

{"title":"Low-Area and Low-Power VLSI Architectures for Long Short-Term Memory Networks","authors":"Mohammed A. Alhartomi;Mohd Tasleem Khan;Saeed Alzahrani;Ahmed Alzahmi;Rafi Ahamed Shaik;Jinti Hazarika;Ruwaybih Alsulami;Abdulaziz Alotaibi;Meshal Al-Harthi","doi":"10.1109/JETCAS.2023.3330428","DOIUrl":"10.1109/JETCAS.2023.3330428","url":null,"abstract":"Long short-term memory (LSTM) networks are extensively used in various sequential learning tasks, including speech recognition. Their significance in real-world applications has prompted the demand for cost-effective and power-efficient designs. This paper introduces LSTM architectures based on distributed arithmetic (DA), utilizing circulant and block-circulant matrix-vector multiplications (MVMs) for network compression. The quantized weights-oriented approach for training circulant and block-circulant matrices is considered. By formulating fixed-point circulant/block-circulant MVMs, we explore the impact of kernel size on accuracy. Our DA-based approach employs shared full and partial methods of add-store/store-add followed by a select unit to realize an MVM. It is then coupled with a multi-partial strategy to reduce complexity for larger kernel sizes. Further complexity reduction is achieved by optimizing decoders of multiple select units. Pipelining in add-store enhances speed at the expense of a few pipelined registers. The results of the field-programmable gate array showcase the superiority of our proposed architectures based on the partial store-add method, delivering reductions of 98.71% in DSP slices, 33.59% in slice look-up tables, 13.43% in flip-flops, and 29.76% in power compared to the state-of-the-art.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"13 4","pages":"1000-1014"},"PeriodicalIF":4.6,"publicationDate":"2023-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135503788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

To Spike or Not to Spike: A Digital Hardware Perspective on Deep Learning Acceleration "秒杀 "还是 "不秒杀"？深度学习加速的数字硬件视角

IF 4.6 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2023-11-06 DOI: 10.1109/JETCAS.2023.3330432

Fabrizio Ottati;Chang Gao;Qinyu Chen;Giovanni Brignone;Mario R. Casu;Jason K. Eshraghian;Luciano Lavagno

{"title":"To Spike or Not to Spike: A Digital Hardware Perspective on Deep Learning Acceleration","authors":"Fabrizio Ottati;Chang Gao;Qinyu Chen;Giovanni Brignone;Mario R. Casu;Jason K. Eshraghian;Luciano Lavagno","doi":"10.1109/JETCAS.2023.3330432","DOIUrl":"10.1109/JETCAS.2023.3330432","url":null,"abstract":"As deep learning models scale, they become increasingly competitive from domains spanning from computer vision to natural language processing; however, this happens at the expense of efficiency since they require increasingly more memory and computing power. The power efficiency of the biological brain outperforms any large-scale deep learning (DL) model; thus, neuromorphic computing tries to mimic the brain operations, such as spike-based information processing, to improve the efficiency of DL models. Despite the benefits of the brain, such as efficient information transmission, dense neuronal interconnects, and the co-location of computation and memory, the available biological substrate has severely constrained the evolution of biological brains. Electronic hardware does not have the same constraints; therefore, while modeling spiking neural networks (SNNs) might uncover one piece of the puzzle, the design of efficient hardware backends for SNNs needs further investigation, potentially taking inspiration from the available work done on the artificial neural networks (ANNs) side. As such, when is it wise to look at the brain while designing new hardware, and when should it be ignored? To answer this question, we quantitatively compare the digital hardware acceleration techniques and platforms of ANNs and SNNs. As a result, we provide the following insights: (i) ANNs currently process static data more efficiently, (ii) applications targeting data produced by neuromorphic sensors, such as event-based cameras and silicon cochleas, need more investigation since the behavior of these sensors might naturally fit the SNN paradigm, and (iii) hybrid approaches combining SNNs and ANNs might lead to the best solutions and should be investigated further at the hardware level, accounting for both efficiency and loss optimization.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"13 4","pages":"1015-1025"},"PeriodicalIF":4.6,"publicationDate":"2023-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135500935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

BioNN: Bio-Mimetic Neural Networks on Hardware Using Nonlinear Multi-Timescale Mixed-Feedback Control for Neuromodulatory Bursting Rhythms BioNN：利用非线性多时间尺度混合反馈控制硬件上的生物仿真神经网络，实现神经调节爆发节奏

IF 4.6 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2023-11-03 DOI: 10.1109/JETCAS.2023.3330084

Kangni Liu;Shahin Hashemkhani;Jonathan Rubin;Rajkumar Kubendran

{"title":"BioNN: Bio-Mimetic Neural Networks on Hardware Using Nonlinear Multi-Timescale Mixed-Feedback Control for Neuromodulatory Bursting Rhythms","authors":"Kangni Liu;Shahin Hashemkhani;Jonathan Rubin;Rajkumar Kubendran","doi":"10.1109/JETCAS.2023.3330084","DOIUrl":"10.1109/JETCAS.2023.3330084","url":null,"abstract":"Biological neurons exhibit rich and complex nonlinear dynamics, which are computationally expensive and area/power hungry for hardware implementation. This paper presents a mathematical analysis and hardware realization of neural networks using a nonlinear neuron model that utilizes two excitable systems operating at different timescales. The neuron consists of a mixed-feedback system operating at multiple timescales to exhibit a variety of modalities that resemble the biophysical mechanisms found in neurophysiology. The single neuron dynamics emerge from four voltage-controlled current sources and feature spiking and bursting output modes that can be controlled using tunable parameters. The bifurcation structures of the neuron, modeled as a 4D dynamical system, illustrate the roles of sources acting on different timescales in shaping neural dynamics. A comprehensive understanding of the system’s dynamic behavior is obtained by studying the state space variables and performing bifurcation analysis on the different parameters. The model is implemented to a 1mm x 2mm prototype chip utilizing the 180nm CMOS process. Each neural network consists of 1 isolated test neuron and 5 fully connected neurons using 20 synapses. By carefully selecting bias voltages according to the I-V characterization curves, the neurons are shown to exhibit spike, burst, and burst excitable behavior. Multiple small-scale neural networks with inhibitory or excitatory synapses were verified to achieve coupled rhythms with neuron bursts in-phase or out-of-phase. To demonstrate an application, the generated burst waveforms from the 4-neuron network were used to form a Central Pattern Generator (CPG) for locomotion control of the four legs of the Petoi, a quadruped robot, enabling the bot to jump successfully.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"13 4","pages":"914-926"},"PeriodicalIF":4.6,"publicationDate":"2023-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134982249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Towards Scalable Digital Modeling of Networks of Biorealistic Silicon Neurons 实现生物现实硅神经元网络的可扩展数字建模

IF 4.6 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2023-11-02 DOI: 10.1109/JETCAS.2023.3330069

Swagat Bhattacharyya;Praveen Raj Ayyappan;Jennifer O. Hasler

引用次数: 0

Design and Analysis of a V-Band CMOS Sextuple SILVCO Using Transformer and Cascade-Series Coupling With a Frequency-Tracking Loop 利用变压器和级联串联耦合以及频率跟踪环路设计和分析 V 波段 CMOS 六倍 SILVCO

IF 4.6 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2023-11-01 DOI: 10.1109/JETCAS.2023.3329430

Wei-Cheng Chen;Hong-Yeh Chang

{"title":"Design and Analysis of a V-Band CMOS Sextuple SILVCO Using Transformer and Cascade-Series Coupling With a Frequency-Tracking Loop","authors":"Wei-Cheng Chen;Hong-Yeh Chang","doi":"10.1109/JETCAS.2023.3329430","DOIUrl":"10.1109/JETCAS.2023.3329430","url":null,"abstract":"A low-phase-noise local oscillator (LO) is a crucial component in communication systems. However, the design challenge of the LO significantly increases as the operating frequency rises. This paper focuses on the design and analysis of a \u0000<inline-formula> <tex-math>$V$ </tex-math></inline-formula>\u0000-band CMOS sextuple sub-harmonically injection-locked voltage-controlled oscillator (SILVCO) with a frequency-tracking loop (FTL). To further enhance the locking range and efficiently generate high-order harmonic components, a cascade-series coupling injector is proposed for employment in the SILVCO. The design methodology of the proposed circuit is thoroughly presented, accompanied by analysis and calculated results. The SILVCO with FTL is implemented using a 90-nm CMOS process. With a sub-harmonic number of 6 and a dc power consumption of 23 mW, the measured output frequency ranges from 50.8 to 53.4 GHz, achieving a differential output power close to 0 dBm. The measured phase noise at a 1 MHz offset and the rms jitter integrated from 1 kHz to 10 MHz are both lower than −109.4 dBc/Hz and 43 fs, respectively.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"14 1","pages":"75-87"},"PeriodicalIF":4.6,"publicationDate":"2023-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135361182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0