IEEE Journal on Emerging and Selected Topics in Circuits and Systems最新文献_第9页

Guest Editorial 2.5D/3D Chiplet Circuits and Systems, EDA, Advanced Packaging, and Test—Part I 客座编辑2.5D/3D芯片电路和系统，EDA，先进封装和测试

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2025-09-16 DOI: 10.1109/JETCAS.2025.3600772

Qinfen Hao;Kuan-Neng Chen;Sandeep Kumar Goel;Hai Li;Erik Jan Marinissen

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IEEE Journal on Emerging and Selected Topics in Circuits and Systems Information for Authors IEEE关于电路和系统信息中新兴和选定主题的作者期刊

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2025-09-15 DOI: 10.1109/JETCAS.2025.3603800

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IEEE Journal on Emerging and Selected Topics in Circuits and Systems IEEE电路与系统中新兴和选定主题杂志

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2025-09-15 DOI: 10.1109/JETCAS.2025.3603804

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IEEE Journal on Emerging and Selected Topics in Circuits and Systems Publication Information IEEE关于电路和系统中新兴和选定主题的期刊出版信息

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2025-09-15 DOI: 10.1109/JETCAS.2025.3603802

引用次数: 0

Research on QC-LDPC Decoding Method With Low Quantization Word Length Based on Adaptive Information Mapping in Passive Optical Network 无源光网络中基于自适应信息映射的低量化字长QC-LDPC译码方法研究

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2025-09-11 DOI: 10.1109/JETCAS.2025.3608825

Tao Zhang;Dehui Kong;Xinwei Fu;Yilin Zhong;Zhaosheng Liu;Renlin Dai;He Shi;Junhui Song

{"title":"Research on QC-LDPC Decoding Method With Low Quantization Word Length Based on Adaptive Information Mapping in Passive Optical Network","authors":"Tao Zhang;Dehui Kong;Xinwei Fu;Yilin Zhong;Zhaosheng Liu;Renlin Dai;He Shi;Junhui Song","doi":"10.1109/JETCAS.2025.3608825","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3608825","url":null,"abstract":"Passive Optical Networks (PON) have advantages such as stable performance, convenient installation, high bandwidth, and resource saving, making them a mainstream network access technology with broad application prospects. The development of such as 8K video, digital twins, VR and other technologies causes explosive growth of network traffic and drives the next generation of PON to evolve towards higher rates, which results in the use of forward error correction (FEC) coding with higher coding gain to improve the power budget of PON. Quasi-cyclic low density parity check (QC-LDPC) codes are widely utilized in PON systems due to high coding gain and parallel encoding and decoding capabilities. However, the application of turbo-decode message passing (TDMP) decoding method is inevitably equated with high hardware complexity of the decoder caused by storing and processing massive information, which is one of the obstacles to PON evolution. Reducing the quantization word length is effective to reduce hardware complexity, but it also leads to saturation of decoding information, causing errors and affecting decoding performance. This work proposes an nonlinear mapping method which utilizes adaptive compression of decoding information through node saturation state monitoring during the decoding process, in order to ensure that the probability density of node information has a reasonable distribution. The simulation results indicate that the method can effectively mitigate the decline in decoding performance under low-word-length conditions.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 1","pages":"5-14"},"PeriodicalIF":3.8,"publicationDate":"2025-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147429278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

System-Technology Co-Optimization Methodology for LLM Accelerators With Advanced Packaging 先进封装LLM加速器的系统技术协同优化方法

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2025-08-07 DOI: 10.1109/JETCAS.2025.3596593

Janak Sharda;Shimeng Yu

{"title":"System-Technology Co-Optimization Methodology for LLM Accelerators With Advanced Packaging","authors":"Janak Sharda;Shimeng Yu","doi":"10.1109/JETCAS.2025.3596593","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3596593","url":null,"abstract":"Recent progress in large language models (LLMs) suggests the feasibility of their deployment on personal devices with model size reduction to a few to dozens of GB. Still, intermediate data’s computing needs are intensive, requiring frequent data reloading from the high-bandwidth memory (HBM). Today’s HBM bandwidth is limited by the number of channels embedded in a 2.5D integrated system. Advanced packaging techniques such as through silicon vias (TSV) and Cu-Cu hybrid bonding (HB) could potentially provide higher bandwidth interconnects between memory and logic dies in a 3D integrated system, where the vertical interconnect can reduce the distance between memory and logic, reducing the total energy consumption. However, this creates a large design exploration space for mixing and matching different packaging techniques and can result in complex thermal management issues due to the proximity of various components. In this work, we describe an evaluation methodology which is used to construct a framework capable of benchmarking system-level power, performance, and area (PPA) metrics for 2.5D/3D integrated systems for LLM accelerators. Additionally, we utilize the framework to conduct a detailed analysis to identify the bottlenecks for training and inference across various models and batch sizes. It is observed that the memory bandwidth and routing energy bottlenecks the inference performance, and the available compute bottlenecks the training performance. Finally, we perform thermal evaluations to observe the trade-off between peak operating temperature and the throughput across different packaging configurations.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 4","pages":"577-584"},"PeriodicalIF":3.8,"publicationDate":"2025-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145808550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Optimizing Thermal Performance in 2.5D Systems Using Embedded Isolators 使用嵌入式隔离器优化2.5D系统的热性能

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2025-08-05 DOI: 10.1109/JETCAS.2025.3595909

George Karfakis;Myriam Bouzidi;Yunhyeok Im;Alexander Graening;Suresh K. Sitaraman;Puneet Gupta

{"title":"Optimizing Thermal Performance in 2.5D Systems Using Embedded Isolators","authors":"George Karfakis;Myriam Bouzidi;Yunhyeok Im;Alexander Graening;Suresh K. Sitaraman;Puneet Gupta","doi":"10.1109/JETCAS.2025.3595909","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3595909","url":null,"abstract":"This paper investigates thermal management in tightly integrated heterogeneous chiplet systems, focusing on a novel approach using embedded thermal isolators. In many 2.5D systems, such as modern enterprise GPUs, thermally sensitive chiplets like High Bandwidth Memory (HBM) are thermally coupled to high-power compute chiplets, leading to performance degradation. We propose and evaluate the use of thermal isolators embedded within the heat spreader to effectively thermally decouple chiplets. Our thermal simulations of a water-cooled 2.5D integrated GPU system indicate that conventional approaches like thermally-aware floorplanning are less effective due to the dominant heat transfer through the heat spreader. In contrast, our proposed thermal isolators can significantly increase thermal isolation between chiplets (by up to 61%), or even reduce overall average peak chip temperature (by up to 22.5%). We develop a closed-loop workflow incorporating thermal results to quantify performance impacts of thermal-induced throttling, finding that in an example GPU+HBM system, the isolator approach can yield performance gains of up to 37% for memory-bound workloads. These findings open up new avenues for thermal management and thermal-system co-optimization in 2.5D heterogeneous integrated systems, potentially enabling more efficient and higher-performing chiplet-based architectures.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 3","pages":"458-468"},"PeriodicalIF":3.8,"publicationDate":"2025-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145061945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

SAFET-HI: Secure Authentication-Based Framework for Encrypted Testing in Heterogeneous Integration 基于安全认证的异构集成加密测试框架

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2025-08-01 DOI: 10.1109/JETCAS.2025.3594675

Galib Ibne Haidar;Jingbo Zhou;Md Sami Ul Islam Sami;Mark M. Tehranipoor;Farimah Farahmandi

{"title":"SAFET-HI: Secure Authentication-Based Framework for Encrypted Testing in Heterogeneous Integration","authors":"Galib Ibne Haidar;Jingbo Zhou;Md Sami Ul Islam Sami;Mark M. Tehranipoor;Farimah Farahmandi","doi":"10.1109/JETCAS.2025.3594675","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3594675","url":null,"abstract":"System-in-Packages (SiPs) are gaining traction due to their enhanced performance, high yield rates, and accelerated time-to-market. However, integrating chiplets from untrusted sources introduces security risks during post-integration testing. Malicious chiplets within the SiP can intercept, modify, or block sensitive test data intended for specific chiplets. This article presents SAFET-HI, a framework designed to ensure a secure testing environment for SiPs. Within this framework, sensitive test data are accessible only to authenticated chiplets. To counter sniffing and spoofing attacks, SAFET-HI encrypts sensitive test patterns while maintaining minimal timing overhead. During post-integration testing, another major threat arises from outsourcing test patterns to untrusted testing facilities, increasing the risk of overproduction and counterfeiting. To address this, SAFET-HI incorporates a functional locking mechanism that prevents unauthorized production and distribution of defective SiPs. Additionally, scan encryption blocks are implemented to stop untrusted test facilities from generating a golden response database. To further enhance security, a watermark bitstream is embedded within the SiP to prevent remarking attacks by untrusted distributors. Simulation results show that SAFET-HI incurs area and timing overheads of only 1.42-4.27% and 13.7%, respectively, demonstrating its effectiveness in securing the SiP testing process.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 3","pages":"478-492"},"PeriodicalIF":3.8,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145061894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Miniaturized and Cost-Effective Programmable 2.5D/3.5D Platforms Enabled by Scalable Embedded Active Bridge Chipset 可扩展嵌入式有源桥芯片组支持小型化和高性价比的可编程2.5D/3.5D平台

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2025-07-30 DOI: 10.1109/JETCAS.2025.3594169

Wei Lu;Jie Zhang;Yi-Hui Wei;Hsu-Ming Hsiao;Sih-Han Li;Chao-Kai Hsu;Chih-Cheng Hsiao;Feng-Hsiang Lo;Shyh-Shyuan Sheu;Chin-Hung Wang;Ching-Iang Li;Yung-Sheng Chang;Ming-Ji Dai;Wei-Chung Lo;Shih-Chieh Chang;Hung-Ming Chen;Kuan-Neng Chen;Po-Tsang Huang

{"title":"Miniaturized and Cost-Effective Programmable 2.5D/3.5D Platforms Enabled by Scalable Embedded Active Bridge Chipset","authors":"Wei Lu;Jie Zhang;Yi-Hui Wei;Hsu-Ming Hsiao;Sih-Han Li;Chao-Kai Hsu;Chih-Cheng Hsiao;Feng-Hsiang Lo;Shyh-Shyuan Sheu;Chin-Hung Wang;Ching-Iang Li;Yung-Sheng Chang;Ming-Ji Dai;Wei-Chung Lo;Shih-Chieh Chang;Hung-Ming Chen;Kuan-Neng Chen;Po-Tsang Huang","doi":"10.1109/JETCAS.2025.3594169","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3594169","url":null,"abstract":"This paper presents the Embedded Multi-die Active Bridge (EMAB) chip, a programmable bridge for cost-effective 2.5D/3.5D packaging technologies. The EMAB chip features a reconfigurable switch array to establish flexible I/O links for connecting multiple chiplets, forming an EMAB chipset based on user needs. It integrates low-dropout regulators (LDOs) for in-package voltage regulation and supports various transmission interfaces, including checkerboard I/Os (50 Mbps–1 Gbps) and MUX I/Os (up to 8 Gbps). Moreover, multiple EMAB chips can be interconnected in a daisy-chain configuration, enabling easy expansion of the EMAB chipset. Additionally, the EMAB chip eliminates TSVs in silicon interposer-based 2.5D packaging technologies and reduces redistribution layer (RDL) complexity through flexible I/O links established within the EMAB chip. Furthermore, EMAB chip can be pre-manufactured as a precast supporting layer (known good die, KGD), which shortens the product development cycle and enhance integration yield. Overall, the EMAB chip offers a miniaturized, low-cost, fast time-to-market and scalable solution for advanced 2.5D/3.5D packaging.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 3","pages":"379-391"},"PeriodicalIF":3.8,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145061909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Enhancing DFT Security in Chiplet-Based Systems With Encryption and Integrity Checking 用加密和完整性检查增强基于芯片系统的DFT安全性

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2025-07-28 DOI: 10.1109/JETCAS.2025.3592984

Juan Suzano;Anthony Philippe;Fady Abouzeid;Giorgio Di Natale;Philippe Roche

{"title":"Enhancing DFT Security in Chiplet-Based Systems With Encryption and Integrity Checking","authors":"Juan Suzano;Anthony Philippe;Fady Abouzeid;Giorgio Di Natale;Philippe Roche","doi":"10.1109/JETCAS.2025.3592984","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3592984","url":null,"abstract":"Chiplet-based chips are the natural evolution of traditional 2D SoCs. In the future, off-the-shelf chiplets are expected to represent an important component of the semiconductor industry. The IEEE Std 1838(TM)-2019 design-for-testability (DFT) standard enable testing of stacked chiplets from multiple vendors. However, the shared DFT network threatens the confidentiality and integrity of test data and other sensitive information. This paper addresses the security concerns associated with DFT infrastructures in chiplet-based systems. We discuss the necessity of securing DFT infrastructures to prevent unauthorized access and malicious activities. Furthermore, we propose a hardware countermeasure that combines encryption and encoding to secure communication over the DFT network. Results show that the DFT can be protected from misbehavior from malicious chiplets on the stack, scan-based attacks, and brute force attacks with minimal overhead in terms of area and test time. The proposed solution causes less than 1% area overhead on designs composed of more than 5 million gates and less than 1% test time overhead for typical DFT implementations.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 3","pages":"493-505"},"PeriodicalIF":3.8,"publicationDate":"2025-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145061903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0