IEEE Journal on Emerging and Selected Topics in Circuits and Systems最新文献_第6页

Securing Weights of CIM-Based Neural Networks Against Power Analysis Attacks 基于cim的神经网络权重防范功率分析攻击

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2026-03-04 DOI: 10.1109/JETCAS.2026.3690257

Fouwad Jamil Mir;Abdullah Aljuffri;Said Hamdioui;Mottaqiallah Taouil

{"title":"Securing Weights of CIM-Based Neural Networks Against Power Analysis Attacks","authors":"Fouwad Jamil Mir;Abdullah Aljuffri;Said Hamdioui;Mottaqiallah Taouil","doi":"10.1109/JETCAS.2026.3690257","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3690257","url":null,"abstract":"Computation-in-Memory (CIM) architectures address the rising demand for energy-efficient artificial intelligence (AI) solutions, by minimizing costly data movements between memory and processor. Within such architectures, SRAM-based digital CIM is especially attractive as it preserves the advantages of CIM while avoiding analog complexity. Recent studies have revealed potential weaknesses in these architectures, particularly to power side-channel attacks (SCA) capable of extracting sensitive model parameters (e.g., neural network (NN) weights), which represent the intellectual property of CIM-based neural network systems. In this study, we propose and evaluate two countermeasures to secure SRAM-based CIM architectures against power attacks: 1) <italic>Balanced Obfuscated-path countermeasure; and 2) <italic>Glitch Aware countermeasure. To validate their effectiveness, we conducted a comprehensive power analysis that successfully demonstrated attacks against an unprotected implementation. Our experimental results demonstrate that both countermeasures significantly improve resistance to power attacks. Although the <italic>Balanced Obfuscated-path offers better area overhead and run-time performance, the <italic>Glitch Aware approach achieves higher protection against advanced attacks, making each suitable for different design constraints.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"549-562"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148433301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Fully Analog Computing-in-Memory Macro With INT8-MAC Operations for Edge-AI Device Edge-AI设备中具有INT8-MAC操作的完全模拟内存计算宏

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2026-01-22 DOI: 10.1109/JETCAS.2026.3657011

Wei-Cheng Huang;Hsin-Ta Chien;Soon-Jyh Chang;Jia-Hao Hu;Chih-Hung Kuo

{"title":"A Fully Analog Computing-in-Memory Macro With INT8-MAC Operations for Edge-AI Device","authors":"Wei-Cheng Huang;Hsin-Ta Chien;Soon-Jyh Chang;Jia-Hao Hu;Chih-Hung Kuo","doi":"10.1109/JETCAS.2026.3657011","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3657011","url":null,"abstract":"Sensors capture large volumes of data containing both critical and redundant information for neural network (NN) inference. However, limited bandwidth and energy efficiency at the sensor-side analog-to-digital conversion (ADC) and data transmission stages significantly increase latency and power consumption in edge devices. Conventional data compression can reduce data volume but cannot distinguish which information is important for the NNs, especially in early layers, where precision is highly sensitive. Such distortions propagate and degrade the overall inference accuracy. To address these challenges, this paper proposes a fully analog computing-in-memory (FACIM) macro that implements and experimentally demonstrates analog-domain feature extraction and inter-layer analog signal propagation mechanisms for NNs. Unlike conventional CIM architectures that rely on inter-layer ADCs, the FACIM concept performs feature extraction directly in the analog domain, thereby reducing early-stage quantization effects and unnecessary data movement. This approach provides a potential pathway toward improved energy efficiency in edge-AI systems. The FACIM macro was fabricated using TSMC 0.18-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m CMOS 1P6M standard technology. It achieves an energy efficiency of 1,880 TOPS/W for INT8 multiply-and-accumulate (MAC) operations and 117 TOPS/W at the system level. The macro demonstrates an area efficiency of 97.76 GOPS/mm2 [normalized macro area (Jhang, 2021)].","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"239-251"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Performance Analysis and Optimization of Fructose Memristor-Based Neuromorphic Systems 基于果糖忆阻器的神经形态系统性能分析与优化

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2026-02-24 DOI: 10.1109/JETCAS.2026.3667550

Harshvardhan Uppaluru;Md Shakil Mahmud Jiban;Shah Zayed Riam;Feng Zhao;Jinhui Wang

{"title":"Performance Analysis and Optimization of Fructose Memristor-Based Neuromorphic Systems","authors":"Harshvardhan Uppaluru;Md Shakil Mahmud Jiban;Shah Zayed Riam;Feng Zhao;Jinhui Wang","doi":"10.1109/JETCAS.2026.3667550","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3667550","url":null,"abstract":"Natural organic memristors have demonstrated promising synaptic behavior, positioning them as strong candidates for synaptic devices in neuromorphic systems. This paper presents the fabrication and evaluation of a neuromorphic system based on natural organic 16-level and 32-level fructose memristors. First, the manufacturing process of fructose memristors is described in detail. Second, the nonlinear property associated with fructose memristors is investigated, and an optimization method is applied to address the nonlinear effects. The performance of the fructose memristor-based neuromorphic system on MNIST with a multi-layer perceptron and on CIFAR-10 with VGG-8 is evaluated and reported under various conditions - with/without nonlinearity optimization and temporal and spatial variations. Without nonlinearity optimization, simulation results on MNIST demonstrate that fructose memristor-based neuromorphic systems achieve average accuracies of 65% for 16-level and 76% for 32-level devices. Applying the nonlinearity optimization has increased the average accuracies to 70% in 16-level and 81% in 32-level devices. On CIFAR-10, maximum test accuracies reach 79%-81% (16-level) and 86%–87% (32-level), but the nonlinearity optimization provides none/minor improvements for 16-level and 32-level devices. Simulations demonstrate 16-level devices are more favorable for edge devices, while 32-level devices are suitable for accuracy-critical tasks. The results presented in this paper demonstrate the potential and viability of the fructose memristor-based neuromorphic systems. The fructose memristor represents a promising addition to sustainable alternatives for neuromorphic systems, encouraging further exploration of natural organic materials.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"157-168"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148513562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

HyIMC: A 16 TOPS/W Hybrid Analog-Digital In-Memory Computing SoC With Model Compression and Recurrent Optimization for Deep Learning-Based Speech Enhancement HyIMC：一种基于深度学习的语音增强模型压缩和循环优化的16 TOPS/W混合模数内存计算SoC

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2026-03-30 DOI: 10.1109/JETCAS.2026.3678971

Wanru Mao;Guangyao Wang;Hanjie Liu;Tianshuo Bai;Jingcheng Gu;Han Zhang;Saiya Wang;Guilin Zhao;Xitong Yang;Aifei Zhang;Xiaohang Wei;Meng Wang;Biao Pan;Wang Kang

{"title":"HyIMC: A 16 TOPS/W Hybrid Analog-Digital In-Memory Computing SoC With Model Compression and Recurrent Optimization for Deep Learning-Based Speech Enhancement","authors":"Wanru Mao;Guangyao Wang;Hanjie Liu;Tianshuo Bai;Jingcheng Gu;Han Zhang;Saiya Wang;Guilin Zhao;Xitong Yang;Aifei Zhang;Xiaohang Wei;Meng Wang;Biao Pan;Wang Kang","doi":"10.1109/JETCAS.2026.3678971","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3678971","url":null,"abstract":"In-memory computing (IMC) presents a promising avenue for deep learning-based speech enhancement (DL-SE). However, the current state-of-the-art IMC architectures are hindered by their inability to simultaneously achieve high precision and energy efficiency, coupled with a lack of parallelism necessary for DL-SE’s distinctive temporal dependency. This paper introduces the HyIMC, which features: 1) analog-digital hybrid IMC architecture that facilitates DL-SE algorithms; 2) schedule controller designed to optimize recurrent dataflow in skip connections; and 3) non-key dimension shrinkage (NKDS), a model compression technique that retains superior accuracy while compressing DL-SE models. Our approach achieves 16 TOPS/W energy efficiency at system-level, implemented on a 40nm eFlash-based IMC SoC prototype. The HyIMC with NKDS compresses DL-SE model size by ~83.3%, enhances the figure of merit by ~1200%, and improves perceptual evaluation of speech quality score by ~120%.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"338-347"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148514134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Scalable Sparse Transformer Accelerator With In-Memory Butterfly Zero Skipper and Local Attention Reusable Engine for Semi-Structured-Pruned NN 基于内存蝶形跳零器和局部注意可重用引擎的半结构剪枝神经网络可扩展稀疏变压器加速器

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2026-02-03 DOI: 10.1109/JETCAS.2026.3660689

Shiwei Liu;Jiangnan Yu;Peizhe Li;Feng Lin;Chixiao Chen

{"title":"Scalable Sparse Transformer Accelerator With In-Memory Butterfly Zero Skipper and Local Attention Reusable Engine for Semi-Structured-Pruned NN","authors":"Shiwei Liu;Jiangnan Yu;Peizhe Li;Feng Lin;Chixiao Chen","doi":"10.1109/JETCAS.2026.3660689","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3660689","url":null,"abstract":"Transformer-based large language models (LLMs) have achieved unprecedented advances across diverse AI tasks. However, their execution remains power-hungry, primarily due to the rapidly growing model size and the quadratic complexity of the self-attention. In-memory computing (IMC) has emerged as a promising solution for accelerating LLMs, delivering high storage density, wide memory bandwidth, and intrinsic compute parallelism. To further improve energy efficiency, this paper addresses LLM inference by leveraging irregular sparse computing in digital SRAM-based IMCs. The proposed butterfly-network-based feed-forward IMC engine enables irregular zero-weight skipping while sustaining high compute utilization. In parallel, a local-attention-reusable IMC engine supports variable sparse attention spans and eliminates redundant self-attention operations. Finally, we implement a four-chip system to scale the parallel performance of the IMC chip. Extensive experiments are deployed on the system, including BERT, GPT to Llama models on 11 AI tasks. The results show that the fabricated accelerator in 28nm CMOS achieves a peak throughput of 186.9 tokens/s and an energy cost of 0.21 J/token, yielding <inline-formula> <tex-math>$4.2times $ </tex-math></inline-formula> speedup and <inline-formula> <tex-math>$27.6times $ </tex-math></inline-formula> energy efficiency over the A100 GPU. Compared to the existing LLM-specific accelerators, the proposed accelerator further achieves <inline-formula> <tex-math>$1.2times $ </tex-math></inline-formula> to <inline-formula> <tex-math>$16.9times $ </tex-math></inline-formula> energy efficiency.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"469-482"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148433138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

In-Memory-Computing for Machine Cognition at the Edge 边缘机器认知的内存计算

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2026-03-02 DOI: 10.1109/JETCAS.2026.3669179

Andreas G. Andreou;Michael Tomlinson;Richard Niu;Adil Malik;Kwesi B. Debrah;Georgios Psaltakis;Daniel R. Mendat;Philippe O. Pouliquen;Jamal L. Molin;Steven Bottone;Sergio Montano;Louise Sengupta;Isidoros Doxas

引用次数: 0

IEEE Journal on Emerging and Selected Topics in Circuits and Systems IEEE电路与系统中新兴和选定主题杂志

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2026-06-15 DOI: 10.1109/JETCAS.2026.3696791

引用次数: 0

Variation-Tolerant Circuit Design and Online Learning Framework for Memristor-Based Trace-STDP SNN 基于忆阻器的Trace-STDP SNN容差电路设计及在线学习框架

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2026-02-11 DOI: 10.1109/JETCAS.2026.3663895

Yi Zheng;Yuhan He;Ruisi Shen;Jie Li;Ruijia Wang;Deyu Wang;Li-Rong Zheng;Zhuo Zou;Jiawei Xu

{"title":"Variation-Tolerant Circuit Design and Online Learning Framework for Memristor-Based Trace-STDP SNN","authors":"Yi Zheng;Yuhan He;Ruisi Shen;Jie Li;Ruijia Wang;Deyu Wang;Li-Rong Zheng;Zhuo Zou;Jiawei Xu","doi":"10.1109/JETCAS.2026.3663895","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3663895","url":null,"abstract":"Spiking neural networks (SNNs) demonstrate significant potential for energy-efficient neuromorphic computing, while trace-based spike-timing dependent plasticity (trace-STDP) serves as a biologically inspired learning rule to improve SNN temporal learning. Memristor-based implementations of trace-STDP SNN leverage device non-linearity to emulate synaptic dynamics, enabling highly energy-efficient computation. However, the mapping from trace-STDP to memristor arrays introduces inherent variations, which significantly degrade network accuracy, posing a critical challenge for the reliable deployment of memristor-based neuromorphic systems. To address this issue, efficient variation-tolerant strategies are essential. However, current approaches do not take the trace-STDP SNN characteristics into consideration, thereby limiting their algorithm- and hardware-level effectiveness. In this work, a variation-aware online learning framework for memristor-based trace-STDP SNN is proposed, with hierarchical simulations integrated across software, ASIC, memristor-array, and memristor-device levels. Through variation analysis experiments, it is observed that variations in near-zero trace values significantly impact network accuracy. To mitigate these effects, a tailored variation-tolerant strategy is developed, together with a configurable hardware clipping unit and an ASIC/memristor co-simulator. The proposed variation-tolerant design achieves up to a 16.97% accuracy improvement, with only a 0.02% extra power overhead and a 0.01% extra area overhead, while a parallel design ensures no additional latency overhead. Integrating the co-simulator into the proposed framework facilitates design space exploration, enhancing the robustness and efficiency of memristor-based neuromorphic computing.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"348-362"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148513723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An HLS-Based Framework for Non-Ideality Aware Modeling of SRAM-Based Analog In-Memory Computing Accelerators 基于hls的sram模拟内存计算加速器非理想感知建模框架

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-06-01 Epub Date: 2026-03-06 DOI: 10.1109/JETCAS.2026.3691005

Talha Bin Aslam;Shivam Shukla;Utkarsh Choudhary;Belal Iqbal;Anuj Grover

{"title":"An HLS-Based Framework for Non-Ideality Aware Modeling of SRAM-Based Analog In-Memory Computing Accelerators","authors":"Talha Bin Aslam;Shivam Shukla;Utkarsh Choudhary;Belal Iqbal;Anuj Grover","doi":"10.1109/JETCAS.2026.3691005","DOIUrl":"https://doi.org/10.1109/JETCAS.2026.3691005","url":null,"abstract":"In-memory computing (IMC) presents a promising solution to mitigate the von Neumann bottleneck in deep neural network (DNN) accelerators, offering significant improvements in energy efficiency by performing computations directly within memory arrays. However, analog IMC architectures based on SRAM are susceptible to various non-idealities that can degrade computational accuracy. Accurately modeling these effects is crucial for design space exploration. This paper proposes a novel High-Level Synthesis (HLS) based framework for the non-ideality-aware modeling and evaluation of SRAM-based analog IMC accelerators. Our framework is composed of three core Intellectual Property (IP) blocks: a behavioral SRAM array model, a behavioral ADC model, and a synthesizable digital shift-and-add block to support multi-bit precision operations. This modular approach provides a direct path from a high-level architectural description to a synthesizable hardware model, incorporating detailed behavioral models for input quantization noise, data-dependent analog non-idealities, and ADC quantization noise. The HLS model characterizes the hardware-induced error as a standard deviation (<inline-formula> <tex-math>$sigma $ </tex-math></inline-formula>) of the Multiply-Accumulate (MAC) output. This hardware-aware error is then injected into a system-level simulation to evaluate the final inference accuracy of various DNNs, including AlexNet, VGG-16, and ResNet-18 on the CIFAR-10 dataset. Our results demonstrate a clear trade-off between hardware parameters (precision, array size) and application-level accuracy, enabling designers to make informed decisions and bridging the critical gap between high level simulation and hardware implementation.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 2","pages":"403-411"},"PeriodicalIF":3.8,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148514063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Guest Editorial Energy-Efficient Optical Communications, Optical Integrated Circuits, and Signal Processing 高能效光通信，光集成电路和信号处理

IF 3.8 2区工程技术

IEEE Journal on Emerging and Selected Topics in Circuits and Systems Pub Date : 2026-03-12 DOI: 10.1109/JETCAS.2026.3664233

Yun Chen;Aseema Mohanty;Keshab K. Parhi

引用次数: 0