纳米级设计中插入 CNT-Via 的延迟受限 GNR 路由选择

IF 3.7 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
Jin-Tai Yan
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引用次数: 0

摘要

众所周知,石墨烯纳米带(GNR)可用作纳米级设计中的互连器件。本文在给定多层路由平面中一组延迟受限的 GNR 网的基础上,通过构建碳纳米管(CNT)/石墨烯组合异质结构来实现相邻两层之间的 CNT 通孔,提出了一种高效的路由算法,以在满足两个 GNR 网之间不交叉约束和带有 CNT 通孔插入的 GNR 路由中 GNR 网的延迟约束的前提下,最大限度地减少所用层数。在初始分配中,根据具有严格延迟约束的 GNR 网的延迟约束路由模式和 GNR 网的延迟约束通路的定义,首先分配延迟约束路由模式以最小化层,然后将延迟驱动的最小长度路由通路和延迟约束通路进一步分配到可用层上。在迭代路由过程中,未路由的 GNR 网可以通过一次迭代迷宫路由和撕裂-向上-路由过程在可用层和一些可能的新层上进一步路由。实验结果表明,与已发表的不插入通孔的路由算法相比,我们提出的插入 CNT 通孔的路由算法可以插入一些 CNT 通孔,并使用更短的线长,在合理的 CPU 时间内,对给定的 GNR 网,在两组不同的延迟约束下,8 个测试实例的平均使用层数分别减少了 53.8% 和 24.9%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Delay-Constrained GNR Routing With CNT-Via Insertion in Nano-Scale Designs
It is well known that graphene nanoribbon (GNR) can be used as interconnects in nano-scale designs. In this paper, given a set of delay-constrained GNR nets in a multiple-layer routing plane, based on the construction of a combined carbon nanotube (CNT)/graphene hetero-structure for CNT-vias between two adjacent layers, an efficient routing algorithm can be proposed to minimize the number of the used layers with satisfying the non-crossing constraints between two GNR nets and the delay constraints on the GNR nets in GNR routing with CNT-via insertion. In the initial assignment, based on the definition of the delay-constrained routing pattern on a GNR net with tight delay constraint and the delay-constrained via path on a GNR net, the delay-constrained routing patterns can be firstly assigned for layer minimization and the delay-driven minimum-length routing paths and the delay-constrained via paths can be further assigned onto the available layers. In the iterative routing, the unrouted GNR nets can be further routed on the available layers and some possible new layers by using one iterative maze-routing and rip-up-and-rerouting process. Compared with the published routing algorithms with no via insertion, the experimental results show that our proposed routing algorithm with CNT-via insertion can insert some CNT-vias and use shorter wirelength to decrease 53.8% and 24.9% of the number of the used layer under reasonable CPU time on the given GNR nets with two different sets of the delay constraints for 8 tested examples on the average, respectively.
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来源期刊
CiteScore
8.50
自引率
2.20%
发文量
86
期刊介绍: The IEEE Journal on Emerging and Selected Topics in Circuits and Systems is published quarterly and solicits, with particular emphasis on emerging areas, special issues on topics that cover the entire scope of the IEEE Circuits and Systems (CAS) Society, namely the theory, analysis, design, tools, and implementation of circuits and systems, spanning their theoretical foundations, applications, and architectures for signal and information processing.
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