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An Evolutionary Approach Based Optimization of Small Signal Parameters for GSDG MOSFET 基于进化方法的GSDG MOSFET小信号参数优化
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179870
Dibyendu Chowdhury, B. P. De, Kanchan Baran Maji, R. Kar, D. Mandal
{"title":"An Evolutionary Approach Based Optimization of Small Signal Parameters for GSDG MOSFET","authors":"Dibyendu Chowdhury, B. P. De, Kanchan Baran Maji, R. Kar, D. Mandal","doi":"10.1109/VLSIDCS47293.2020.9179870","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179870","url":null,"abstract":"This paper present the optimization of small- signal parameters for GSDG (Gate Stack Double Gate) MOSFET in deep submicron analogue circuit design. The evolutionary optimization algorithms taken for this study are CRPSO (Craziness-based Particle Swarm Optimization) and ALCPSO (Aging Leader Challenger based PSO). The small-signal parameters like trans-conductance, OFF-state current and different other design parameters of GSDG MOSFET are optimized in the regions of sub-threshold and saturation from the above mentioned evolutionary techniques to achieve the superior electrical performance of the MOSFET in the analogue domain. The results obtained from ALCPSO and CRPSO techniques are much improved as compared with the results of preceding literature and may be considered for the useful device design.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133681976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Analytical Drain Current Model for Super-Threshold Region of Double Gate Tunnel FET 双栅隧道场效应管超阈区漏极电流解析模型
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179867
Joy Chowdhury, A. Sarkar, K. Mahapatra, J. Das
{"title":"Analytical Drain Current Model for Super-Threshold Region of Double Gate Tunnel FET","authors":"Joy Chowdhury, A. Sarkar, K. Mahapatra, J. Das","doi":"10.1109/VLSIDCS47293.2020.9179867","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179867","url":null,"abstract":"To support miniaturization and low power demands of the electronic systems market, the essential scaling laws are marred due to performance degradation by Short Channel Effects. The recently developed TFETs follow interband tunneling (BTBT) as their current injection mechanism and have better subthreshold swing (below 60mV/dec) compared to the conventional SOI MOSFETs. This article presents an analytical model for drain current in the super threshold region. The parabolic potential approach is used including the effect of fringing fields and mobile charges in the channel. This model predicts the surface potential, electric field and BTBT current with reasonable accuracy, thus reflecting most of the physical device phenomena.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132347513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Performance Analysis of Ni3GeFe2 / Fe3GeTe2 Composites as Ferromagnetic Layer in MTJ Memory Devices Ni3GeFe2 / Fe3GeTe2复合材料作为MTJ存储器件中铁磁层的性能分析
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179854
Bibek Chettri, Bindiya Sharma, Abinash Thapa, P. Chettri, B. Sharma
{"title":"Performance Analysis of Ni3GeFe2 / Fe3GeTe2 Composites as Ferromagnetic Layer in MTJ Memory Devices","authors":"Bibek Chettri, Bindiya Sharma, Abinash Thapa, P. Chettri, B. Sharma","doi":"10.1109/VLSIDCS47293.2020.9179854","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179854","url":null,"abstract":"The studies were performed based on various composites to improve the features of Magnetic Tunnel Junction (MTJ) memory devices. We have studied the electrical and electronic properties of Ni<inf>3</inf>GeFe<inf>2</inf> and Fe<inf>3</inf>GeTe<inf>2</inf>. MgO-hBN-MgO is used as a composite dielectric material. The ferromagnetic material Ni<inf>3</inf>GeFe<inf>2</inf> and Fe<inf>3</inf>GeTe<inf>2</inf> have shown improvement in various electronic and magnetic properties that can be useful for further implementation in MTJ device. The Ni<inf>3</inf>GeFe<inf>2</inf> and Fe<inf>3</inf>GeTe<inf>2</inf> predicted good magneto-transport property that characterizes their ferromagnetic state. In oxide layer the direct bandgap of 1.0437eV at Gamma point is obtained. The validation of Ni<inf>3</inf>GeFe<inf>2</inf> and Fe<inf>3</inf>GeTe<inf>2</inf> as ferromagnetic layer is predicted as it showed 0eV bandgap. Local Density of State (LDOS) of FM and oxide layer is calculated along with it the electron transport is observed in z direction. It is found that these two ferromagnetic (FM) materials showed a high Curie temperature. The DOS and Band Structure of Fe is compared with Ni<inf>3</inf>GeFe<inf>2</inf>, Fe<inf>3</inf>GeTe<inf>2</inf>. In comparison with the DOS of Fe showed peak at the valance band i.e. 0.45eV and 0.69eV which shows instability of memory states, as in case of Ni<inf>3</inf>GeFe<inf>2</inf> and Fe<inf>3</inf>GeTe<inf>2</inf> (stable FM materials) the peaks were observed is conduction band. The study depicts that Ni<inf>3</inf>GeFe<inf>2</inf> and Fe<inf>3</inf>GeTe<inf>2</inf> are promising candidate for its implementation in MTJ memory device. As they show better edge boundaries and good stability of states.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115534757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The Effect of Gate Stack and High-ĸ Spacer on Device Performance of a Junctionless GAA FinFET 栅极堆叠和高阶间隔对无结GAA FinFET器件性能的影响
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179855
Bhavya Kumar, Ajay Kumar, R. Chaujar
{"title":"The Effect of Gate Stack and High-ĸ Spacer on Device Performance of a Junctionless GAA FinFET","authors":"Bhavya Kumar, Ajay Kumar, R. Chaujar","doi":"10.1109/VLSIDCS47293.2020.9179855","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179855","url":null,"abstract":"In this work, we investigated the effect of the gate stack and high-ĸ gate spacers on the digital and analog performance of a lightly doped n-type Si channel Junctionless Rectangular Gate All Around (JL-Re-GAA) FinFET. Different digital and analog parameters, for instance, drain current (Id), leakage current (Ioff), switching ratio (Ion/Ioff), subthreshold swing (SS), transconductance (gm), output conductance (gd), transconductance generation factor (TGF), intrinsic gain (Av), early voltage (VEA) have been analyzed. From the simulated results obtained, we have found that the use of gate stack and high-ĸ gate spacers remarkably improves the digital and analog figures of merits (FOMs) of the device. Thus, the JL-Re-GAA FinFET structure with high-k gate spacers and gate stack can be considered as a suitable candidate in digital and analog circuit applications.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114363668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Low-power and Area Efficient Approximate Multiplier with Reduced Partial Products 减少部分积的低功耗和面积效率近似乘法器
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179923
M. Sukla, K. Sethi, A. Panda
{"title":"Low-power and Area Efficient Approximate Multiplier with Reduced Partial Products","authors":"M. Sukla, K. Sethi, A. Panda","doi":"10.1109/VLSIDCS47293.2020.9179923","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179923","url":null,"abstract":"Need of approximate computing has increased to the pinnacle for error-tolerant applications. This leads to further optimization in terms of power and area with remarkable enhancement in computational speed within an acceptable error range. So, the performance and the error characteristic are considered with equal importance. This work presents a power and area optimized architecture for error-tolerant multiplier. A trade-off is made with the error characteristic by using approximation at the lower stage of partial product. Results for area, power and error factor are shown for range of multipliers. A significant improvement is achieved by using the proposed technique. The logics are implemented using 45nm process technology and Cadence GENUS™ Synthesis Solution. The synthesis environment is set to slow_vdd1v0 at operating conditions PVT_1P1V_0C (balanced tree).","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114776082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Charge Transfer Mechanism of Gallium Nitrite/Reduced Graphene Oxide (GaN/rGO) Nanocomposite 亚硝酸镓/还原氧化石墨烯纳米复合材料的电荷转移机理
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179877
Sumitra Nongthombam, Sayantan Sinha, N. A. Devi, S. Rai, R. Bhujel, W. I. Singh, Bibhu Prasad Swain
{"title":"Charge Transfer Mechanism of Gallium Nitrite/Reduced Graphene Oxide (GaN/rGO) Nanocomposite","authors":"Sumitra Nongthombam, Sayantan Sinha, N. A. Devi, S. Rai, R. Bhujel, W. I. Singh, Bibhu Prasad Swain","doi":"10.1109/VLSIDCS47293.2020.9179877","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179877","url":null,"abstract":"An in-situ chemical reduction method was followed to produce reduced graphene oxide/gallium nitride (rGO/GaN) nanocomposites using GaN powder and graphene oxide as raw materials. The morphological, structural, chemical bonding, optical properties, chemical bonding network and compositional analysis were performed using SEM, XRD, FTIR, UV-Vis, Raman and XPS spectroscopy respectively. The particle size and crystallite size of the rGO/GaN nanocomposite were calculated as 152-207 nm and 31.7 nm respectively. The Raman spectra of rGO/GaN nanocomposite reveal a blue shift of 3.18 cm-1 of the E2 (high) peak of GaN. Electrical properties of rGO/GaN nanocomposites coated over Indium Tin Oxide were analyzed with current-voltage characterization. The nanocomposite shows diode characteristics at a higher voltage in the forward and reverses bias. Moreover, a very low leakage currents up to the cut off voltage 1V was observed in the reverse bias.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114479650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Advantages of Charge Plasma Based Double Gate Junctionless MOSFET Over Bulk MOSFET for Label Free Biosensing 基于电荷等离子体的双栅无结MOSFET在无标签生物传感中的优势
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179747
Amit Bhattacharyya, Adrija Mukherjee, M. Chanda, D. De
{"title":"Advantages of Charge Plasma Based Double Gate Junctionless MOSFET Over Bulk MOSFET for Label Free Biosensing","authors":"Amit Bhattacharyya, Adrija Mukherjee, M. Chanda, D. De","doi":"10.1109/VLSIDCS47293.2020.9179747","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179747","url":null,"abstract":"An assessment of charge plasma (CP) based biosensing between junction less (JL) and conventional devices for label-free electrical identification of analytes, especially DNA, has been examined here in detail. The impact of variations of charge analytes immobilized inside the nanogap cavity over the drain current, energy band profile, electron concentration, and sensitivity evaluated in dry atmospheric conditions. Here, the shifts into threshold potential for both JL-MOSFET and conventional-MOSFET based biosensor architecture have been utilized, like the sensing factor, to identify the existence of analytes while they immobilized inside the nanogap cavity in the channel section. The design of the recommended model with the complete numerical analysis has been executed utilizing the ATLAS device simulation software.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122816939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Intellectual Completion Tracking System Micro-architecture for Advanced NoC Designs 面向高级NoC设计的智能完井跟踪系统微架构
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179889
Sudeep P, Naveen Kanumuri, Sreenath Ak, Vadlamuri Venkata Sateesh
{"title":"Intellectual Completion Tracking System Micro-architecture for Advanced NoC Designs","authors":"Sudeep P, Naveen Kanumuri, Sreenath Ak, Vadlamuri Venkata Sateesh","doi":"10.1109/VLSIDCS47293.2020.9179889","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179889","url":null,"abstract":"The increase in the number of processing elements on network-on-chip (NoC) demands high throughput and low latency with constraints on the area of the chip. Network Interface (NI) is one of the fundamental and performance-hungry blocks in an NoC. NI is responsible for handling acknowledgments for its requests. To handle acknowledgments in an NI, NoC must have a Completion Tracking System block. Completion Tracking System with static queues is prone to huge areas and low throughput. This paper presents an Intellectual Completion Tracking System (ICTS) which can handle multiple outstanding transactions from different initiators and assists in generating the responses from network interfaces, which caters to the network interface between PCI interfaces and nonstandard PCI interfaces.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"4 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123895159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
VLSI DCS 2020 Messsage from Chair and Others 来自主席和其他人的VLSI DCS 2020消息
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/vlsidcs47293.2020.9179911
{"title":"VLSI DCS 2020 Messsage from Chair and Others","authors":"","doi":"10.1109/vlsidcs47293.2020.9179911","DOIUrl":"https://doi.org/10.1109/vlsidcs47293.2020.9179911","url":null,"abstract":"","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123986328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Attenuation Modelling and Machine Learning Based SNR Estimation for 5G Indoor Link 基于衰减建模和机器学习的5G室内链路信噪比估计
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179924
M. A. Islam, Manabendra Maiti, Quazi Md. Alfred, Pradip Kumar Ghosh, J. Sanyal
{"title":"Attenuation Modelling and Machine Learning Based SNR Estimation for 5G Indoor Link","authors":"M. A. Islam, Manabendra Maiti, Quazi Md. Alfred, Pradip Kumar Ghosh, J. Sanyal","doi":"10.1109/VLSIDCS47293.2020.9179924","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179924","url":null,"abstract":"A significant number of propagation models have been proposed for 5G communication systems in recent years. Among the different environments studied, indoor propagation environments have emerged in importance. The present paper reviews current research in indoor propagation modelling at different frequencies relevant to 5G signal propagation. The paper goes on to present a model for attenuation of 5G signals in the X band. The model takes into account the variation of signal attenuation due to varying number of human bodies and other obstacles present in the indoor environment at different times of a day, leading to time-dependent difference in signal to noise ratio (SNR). A non-linear polynomial based machine learning technique is then used to obtain a least-squares (LS) estimate of SNR from the model.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126011394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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