2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)最新文献_第4页

Design of Low power & High Performance Multi Source H-Tree Clock Distribution Network 低功耗高性能多源h树时钟配电网设计

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179954

Srivatsa V G, A. Chavan, Divakar Mourya

引用次数: 5

Power Allocation in NOMA Using Cournot Game Theory 基于古诺博弈论的NOMA中的权力分配

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179875

Aritra De, Tirthankar Datta

引用次数: 0

Harmonic Compensation for Nonlinear Loads Fed by Grid Connected Solar Inverters Using Active Power Filters 利用有源滤波器对并网太阳能逆变器非线性负荷进行谐波补偿

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179882

S. Mukherjee, S. Mazumder, S. Adhikary

引用次数: 1

Intelligent Energy Management Systems for Optimal Techno-Commercial Benefit in DC Micro-grids: A Review 基于智能能源管理系统的直流微电网技术-商业效益优化研究进展

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179910

Birendra Krishna Ghosh, Sawan Sen, Sandip Chanda

{"title":"Intelligent Energy Management Systems for Optimal Techno-Commercial Benefit in DC Micro-grids: A Review","authors":"Birendra Krishna Ghosh, Sawan Sen, Sandip Chanda","doi":"10.1109/VLSIDCS47293.2020.9179910","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179910","url":null,"abstract":"The demand for clean, high quality and low rate Electrical Energy is on rising scale in the last decade. Both the traditional ways of generating power and delivering the same through long transmission lines are less appreciated due to the cost associated and also the detrimental effects on environment. Renewable Energy Sources (RES) may be achieved clean if smart integration of the same. Present micro-grids are supported by energy management systems (EMS) which only optimise resource management to supply continuous power to the consumers. The economic considerations such as costing profile of the sources, demand response and price discovery along with technological considerations like power quality assessment and standardisation is however, absent in these systems. Moreover, the EMS developed are location and operational condition specific that is these EMS cannot be programmed as per the requirement of the user. Hence the present EMS in use, in islanded or off-grid condition may not select the appropriate source to cater the demand requested and also is not flexible enough. Also the EMS can be developed in a way that all the information and constraints can be programmed in it. Some optimisation techniques can be used to solve the objective function. In addition to this, the intelligent EMS is proposed to improve the power quality by continuously monitoring a few standard performance indices. Though the work is based on off grid independent micro grid but the EMS will be developed with such an algorithm for both mode of operation -islanded and conventional so that which can provide benefits for off-grid operations also.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129385162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

FPGA Implementation of Symmetric Systolic FIR Filter using Multi-channel Technique 基于多通道技术的对称收缩FIR滤波器的FPGA实现

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179926

Debarshi Datta, Sahil Akhtar, H. Dutta

{"title":"FPGA Implementation of Symmetric Systolic FIR Filter using Multi-channel Technique","authors":"Debarshi Datta, Sahil Akhtar, H. Dutta","doi":"10.1109/VLSIDCS47293.2020.9179926","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179926","url":null,"abstract":"High performance Finite Impulse Response (FIR) filters are extensively used in digital signal processing (DSP), communications, image processing and many more areas. This paper approaches Field Programmable Gate Arrays (FPGAs) based on systolic FIR architectures using multi-channel technique with symmetric coefficients to ensure faster response and optimum area. The embedded Digital Signal Processing (DSP) blocks for its multiply-accumulator (MAC) perform accurate operations where the filter architecture is efficiently realized in the reconfigurable hardware platform. The characteristics of systolic FIR architecture are synchrony, modularity and regularity to make a perfect filter design. Also its pipeline structure provides high throughput and symmetric technique reduces the memory size. Both of these techniques improve the overall performance of the FIR architecture in FPGA domain. The proposed FIR architecture has been successfully verified by Xilinx ISE 14.7 tool and then implemented on Virtex-5 FPGA board. The design method shows a great improvement of maximum operating frequency and save the area as compared to the earlier architectures.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116097358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Comparative Study of Doublet OTA Circuit Topologies Operating in Weak Inversion Mode for Low Power Analog IC Applications 低功耗模拟集成电路弱反转双重态OTA电路拓扑的比较研究

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179858

Rishov Aditya, Saheli Sarkel, Soumya Pandit

引用次数: 0

Design of Modified Grounded Microstrip Antenna for Dual Band Operation in Wireless Communication 用于无线通信双频工作的改进接地微带天线设计

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179936

Avisankar Roy, S. Mukherjee, S. Bhunia

引用次数: 1

Effect of Body Thickness on Device Performance of Graded Channel Tri-Metal Double Gate Stack Gate TFET 体厚对梯度沟道三金属双栅堆叠栅极TFET器件性能的影响

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179899

Sudipta Ghosh, S. Kundu, S. Guha, J. Ghosh, Prithviraj Pachal, S. Sarkar

{"title":"Effect of Body Thickness on Device Performance of Graded Channel Tri-Metal Double Gate Stack Gate TFET","authors":"Sudipta Ghosh, S. Kundu, S. Guha, J. Ghosh, Prithviraj Pachal, S. Sarkar","doi":"10.1109/VLSIDCS47293.2020.9179899","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179899","url":null,"abstract":"In this work the authors presented a 2-D analytical drain current model of graded channel tri-metal double gate (TMDG) TFET with stacked gate-oxide structure. The parabolic approximation method with suitable boundary conditions has been applied to solve Poisson’s equation of surface potential in the channel region. Therefor the tunneling generation rate is integrated over source-channel junction area to derive the drain current expression. The proposed model demonstrates the impact of graded channel as a potential barrier at the channel region to reduce leakage current in OFF state and as well as in ON state. High doping concentration at the junction of source and channel boosts up band-to-band tunneling, which reduces subthreshold slope consequently. Proper choice of work function for the gate electrodes gives better results in terms of ION/IOFF ratio and SS. The stack gate structure provides better gate control over channel region with lesser leakage current. The explanatory aftereffects of the proposed model have been approved against the TCAD reproduction information in this work.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123655281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Stability of Hybrid SET-CMOS Based NOT Gate 基于SET-CMOS的混合非门稳定性研究

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179937

Arpita Ghosh

引用次数: 1

VLSI DCS 2020 Author Index VLSI DCS 2020作者索引

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/vlsidcs47293.2020.9179953

引用次数: 0