2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)最新文献

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FPGA Implementation of WRVFLN for Classification WRVFLN分类的FPGA实现
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179940
S. K. Rout, M. Sahani, Bhanja Kishor Swain, Pradyut Kumar Biswal
{"title":"FPGA Implementation of WRVFLN for Classification","authors":"S. K. Rout, M. Sahani, Bhanja Kishor Swain, Pradyut Kumar Biswal","doi":"10.1109/VLSIDCS47293.2020.9179940","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179940","url":null,"abstract":"Now-a-days, field programmable gate array (FPGA) is used in various domain of research to design a computer-aided-diagnosis (CAD) system to classify the data in real-time. In this paper, weighted random vector functional link network (WRVFLN) is presented and implemented on a fast FPGA hardware platform to classify the data. The WRVFLN classifier produces better data classification accuracy in comparison to other existing prevalent methods. The remarkable data classification accuracy and faster learning speed of the WRVFLN classifier facilitates the hardware implementation of WRVFLN classifier. Moreover, the developed digital architecture of WRVFLN classifier is employed on a Xilinx Virtex-5 (ML506) FPGA hardware environment, aid to construct an embedded system for real-time data classification.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116396570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
EEG Based Mental Arithmetic Task Classification Using a Stacked Long Short Term Memory Network for Brain-Computer Interfacing 基于堆叠长短期记忆网络的脑机接口脑电心算任务分类
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179949
Biswarup Ganguly, Arpan Chatterjee, Waqar Mehdi, Soumyadip Sharma, S. Garai
{"title":"EEG Based Mental Arithmetic Task Classification Using a Stacked Long Short Term Memory Network for Brain-Computer Interfacing","authors":"Biswarup Ganguly, Arpan Chatterjee, Waqar Mehdi, Soumyadip Sharma, S. Garai","doi":"10.1109/VLSIDCS47293.2020.9179949","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179949","url":null,"abstract":"This paper proposes an electroencephalogram (EEG) based mental arithmetic task classification using a stacked long short-term memory (LSTM) architecture for brain computer interfacing (BCI). EEG signals from 22 channels are taken from 36 subjects, as mentioned in the Physionet database. A deep learning framework based on LSTM is employed to identify and classify the mental arithmetic task by reducing the number of electrodes. Window segmentation is applied for data augmentation as well as feature extraction from all the recorded EEG signals. Eight features per electrode have been fed into the proposed LSTM architecture. The main aspect of this network along with the dropout layers is to enhance feature learning ability and to avoid over fitting.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114569180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Design and Implementation of Eye Pupil Movement Based PIN Authentication System 基于眼球瞳孔运动的PIN认证系统的设计与实现
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179933
Indrajit Das, Ria Das, Shalini Singh, Amogh Banerjee, Md Golam Mohiuddin, Avirup Chowdhury
{"title":"Design and Implementation of Eye Pupil Movement Based PIN Authentication System","authors":"Indrajit Das, Ria Das, Shalini Singh, Amogh Banerjee, Md Golam Mohiuddin, Avirup Chowdhury","doi":"10.1109/VLSIDCS47293.2020.9179933","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179933","url":null,"abstract":"PINs (Personal Identification Systems) have been widely adopted worldwide as primary means of secure communication for user authentication and verification purposes. However, it’s not a foolproof system since it can be easily forged. Since PINs needs to be entered manually, it provides an easy opportunity for an intruder to crack it. Thus it is susceptible to various intrusions such as shoulder surfing, key logger, tap print etc. In this paper, an eye pupil movement based PIN generation system has been devised. At first, the user enters sensitive authentication input (PIN) by using eye pupil movements in various directions (i.e. Left, Middle and Right), which further is internally mapped into various pattern of digits from 0 to 9. Thus eavesdropping by a malicious observer becomes practically impossible. It utilizes Haar-Cascade classifier for face and eye detection followed by combined approach of HOG features integrated with SVM classifier for eye blink detection. For pupil detection, canny operator is employed followed by fitting a circle to pupil using circular Hough Transform. Tracking the position of eye pupil is achieved using projection function algorithm. The accuracy of eye detection, eye blink detection and eye tracking is 98%, 92.51 % and 96.25 % respectively. The contribution of this paper is outlined along with a comparative study between proposed approach and traditional authentication systems like gaze, gaze – touch, eye movement CAPTCHA and such graphical image based authentication methodologies. Our devised system is simple, user friendly and works under low light conditions without involving any significant dependencies on the intricacies of the system.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"195 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114974959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low Power Quaternary Adder Using CNFET 采用CNFET的低功率四元加法器
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179898
Anurag Chauhan, Lokesh Mahor, P. Tiwari
{"title":"Low Power Quaternary Adder Using CNFET","authors":"Anurag Chauhan, Lokesh Mahor, P. Tiwari","doi":"10.1109/VLSIDCS47293.2020.9179898","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179898","url":null,"abstract":"Binary logic and MOS devices have been in use since the inception of the design era, but now due to advancement in VLSI industry binary logic has become tedious and complicated. To overcome this challenge Multi-valued logic (MVL) such as ternary and Quaternary Logic (QTL) can be used. MVL designs have an advantage over binary logic designs with respect to the chip area and the complexity of interconnection. In this paper, we present the design and performance analysis of QTL Full Adder (QFA) using Carbon Nano-tube Field Effect Transistor (CNFET). For design purposes, we have used the Stanford Virtual-Source Carbon Nanotube Field Effect Transistor Model version 1.01 with sub 10nm CNFET technology. The design tool used for simulation is Cadence Virtuoso. The proposed QFA design has been compared against the existing CNFET based QTL designs and it is found that the proposed QFA design is 97-98% better in terms of Power Delay Product (PDP) and Energy Delay Product.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133575955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Synthesis and Characterization of Fe Doped CdS Quantum Dot 掺铁CdS量子点的合成与表征
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179941
A. Ganguly, V. Srivastava
{"title":"Synthesis and Characterization of Fe Doped CdS Quantum Dot","authors":"A. Ganguly, V. Srivastava","doi":"10.1109/VLSIDCS47293.2020.9179941","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179941","url":null,"abstract":"Transition metal ion doped quantum dots finds their wide range of use in the field of photonics and photovoltaics. In this research work, CdS quantum dots, with Fe ion doping, are synthesized using simple One Pot Synthesis chemical method. The polymer matrix used in the synthesis is Polyvinyl Alcohol (PVA) matrix, which restricts the size of quantum dot while not itself participating in the reaction. Three doping concentrations are 3%, 6%, and 9%, by weight of Fe have been used for doping of CdS. The synthesized quantum dots are also analyzed using Ultraviolet Visible (UV-Vis) Absorption, X-Ray Diffraction (XRD), and HRTEM microscopy to study their optical and crystallographic properties.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"124 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133678890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improved Loss Characteristic in 1-bit RF MEMS Switch owing to Lower Dielectric Constant 低介电常数改善1位射频MEMS开关损耗特性
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179874
P. Debnath, A. Deyasi, Ujjwal Mondai, A. Sarkar
{"title":"Improved Loss Characteristic in 1-bit RF MEMS Switch owing to Lower Dielectric Constant","authors":"P. Debnath, A. Deyasi, Ujjwal Mondai, A. Sarkar","doi":"10.1109/VLSIDCS47293.2020.9179874","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179874","url":null,"abstract":"Lower return loss and isolation loss of 1-bit RF MEMS switch is analytically investigated for different dielectric materials over the L band to K band. Both unactuated as well as actuated conditions are taken care for simulation purpose, where overlap area is kept constant. Simulated findings reveal that both the losses are significantly reduced for lower dielectric constant material (SiO2) compared to higher permittivity (Si3N4) upto 30% which is an indirect estimation for measuring upstate and down-state capacitances. Results are also compared with existing data from published literature which speaks in favor of the present work for phase-shifter design.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132979370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of Graded Back-Barrier on Linearity of Recessed Gate InAlN/GaN HEMT 梯度背势垒对嵌入式栅InAlN/GaN HEMT线性度的影响
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179897
Megha Sharma, R. Chaujar
{"title":"Impact of Graded Back-Barrier on Linearity of Recessed Gate InAlN/GaN HEMT","authors":"Megha Sharma, R. Chaujar","doi":"10.1109/VLSIDCS47293.2020.9179897","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179897","url":null,"abstract":"Work presented in this paper reports the impact of graded AlGaN back-barrier on the linearity performance of lattice-matched InAlN/AlN/GaN recess gate device. Specifically, a comparison is made on the linearity of the proposed device with and without a graded back barrier layer. Various device performance matrices namely transconductance (gm) and its higher-order derivatives, second and third-order voltage intercept point (VIP2, VIP3), 3rd order input intercept point (IIP3), 3rd inter-modulation distortion (IMD3) and 1-dB compression point have been investigated and discussed for the proposed device architecture. Results obtained from TCAD simulation of the proposed device confirms that by using graded back-barrier the linearity performance matrices of the device are improved, which further shows that the proposed device is also suitable for wireless applications.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"289 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123451310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Kerr Nonlinearity Effect on Dimensionless Scalar and Vector Propagation Constants of Single-Mode Graded Index Fiber: Estimation by a Simple but Accurate Method 克尔非线性对单模梯度折射率光纤无因次标量和矢量传播常数的影响:一种简单而准确的估计方法
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179865
Tilak Mukherjee, Angshuman Majumdar, S. Gangopadhyay
{"title":"Kerr Nonlinearity Effect on Dimensionless Scalar and Vector Propagation Constants of Single-Mode Graded Index Fiber: Estimation by a Simple but Accurate Method","authors":"Tilak Mukherjee, Angshuman Majumdar, S. Gangopadhyay","doi":"10.1109/VLSIDCS47293.2020.9179865","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179865","url":null,"abstract":"A simple but accurate power series expression for fundamental mode of single- mode graded index fiber is employed here for the estimation of dimensionless scalar and vector propagation constants in presence and absence of Kerr non linearity. Chebyshev formalism is employed for the formulation of the power series. In case of concerned prediction in presence of Kerr non linearity, the formalism requires application of method of iteration. Single -mode parabolic index profile fibers with appropriate V number values are considered for our present study. Our results match well with exact results obtained using rigorous finite element method. Our formalism essentially needs considerably less computation. Thus, our simple but accurate formalism can further be extended in the analysis of other nonlinear fibers and their propagation characteristics.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"257 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122826049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multi Input Single Output using Operational Transresistance Amplifier as First Order Filter 采用运算跨阻放大器作为一阶滤波器的多输入单输出
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179938
K. Banerjee, Prasit Kumar Bnadopadhyaya, Bishal Sarkar, A. Biswas
{"title":"Multi Input Single Output using Operational Transresistance Amplifier as First Order Filter","authors":"K. Banerjee, Prasit Kumar Bnadopadhyaya, Bishal Sarkar, A. Biswas","doi":"10.1109/VLSIDCS47293.2020.9179938","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179938","url":null,"abstract":"The following research paper gives a different type of voltage mode multifunction filter which is of first order, which consist of only one OTRA block that is operational transresistance amplifier and few of the passive components. This structure can be used for employing different types of filter functions of 1st order. The proposed device is simulated with the parameters of 0.5µm CMOS which is defined by MOSIS (AGILENT). The results are verified using simulation software PSPICE.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115386047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Design of 3:2 Compressor Using Quantum Dot Cellular Automata 基于量子点元胞自动机的3:2压缩机设计
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS) Pub Date : 2020-07-01 DOI: 10.1109/VLSIDCS47293.2020.9179930
B. Debnath, J. Das, D. De
{"title":"Design of 3:2 Compressor Using Quantum Dot Cellular Automata","authors":"B. Debnath, J. Das, D. De","doi":"10.1109/VLSIDCS47293.2020.9179930","DOIUrl":"https://doi.org/10.1109/VLSIDCS47293.2020.9179930","url":null,"abstract":"Quantum-dot Cellular Automata (QCA) design is a promising technology for the nano-scale implementation of digital systems. It is a framework with low power utilization and a potentially high compactness. QCA promotes nanotechnology architecture for new devices. This system works on the basis of electron interactions within quantum dots that contribute to the emergence of quantum properties and reduces the problem of size for generation of future circuits. In this article 3:2 compressor is designed dependent on QCA with the less area, delay and intricacies. A 2-input XOR gate is used and a 2:1 multiplexer are used to propose the encoder. Thereafter it is extended to construct 3:2 compressor. The circuit proposed is constructed using the QCA Designer tool. Practical results are consistent with the principle that explains the suitability of the QCA circuitry.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128136224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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