{"title":"梯度背势垒对嵌入式栅InAlN/GaN HEMT线性度的影响","authors":"Megha Sharma, R. Chaujar","doi":"10.1109/VLSIDCS47293.2020.9179897","DOIUrl":null,"url":null,"abstract":"Work presented in this paper reports the impact of graded AlGaN back-barrier on the linearity performance of lattice-matched InAlN/AlN/GaN recess gate device. Specifically, a comparison is made on the linearity of the proposed device with and without a graded back barrier layer. Various device performance matrices namely transconductance (gm) and its higher-order derivatives, second and third-order voltage intercept point (VIP2, VIP3), 3rd order input intercept point (IIP3), 3rd inter-modulation distortion (IMD3) and 1-dB compression point have been investigated and discussed for the proposed device architecture. Results obtained from TCAD simulation of the proposed device confirms that by using graded back-barrier the linearity performance matrices of the device are improved, which further shows that the proposed device is also suitable for wireless applications.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"289 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Impact of Graded Back-Barrier on Linearity of Recessed Gate InAlN/GaN HEMT\",\"authors\":\"Megha Sharma, R. Chaujar\",\"doi\":\"10.1109/VLSIDCS47293.2020.9179897\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Work presented in this paper reports the impact of graded AlGaN back-barrier on the linearity performance of lattice-matched InAlN/AlN/GaN recess gate device. Specifically, a comparison is made on the linearity of the proposed device with and without a graded back barrier layer. Various device performance matrices namely transconductance (gm) and its higher-order derivatives, second and third-order voltage intercept point (VIP2, VIP3), 3rd order input intercept point (IIP3), 3rd inter-modulation distortion (IMD3) and 1-dB compression point have been investigated and discussed for the proposed device architecture. Results obtained from TCAD simulation of the proposed device confirms that by using graded back-barrier the linearity performance matrices of the device are improved, which further shows that the proposed device is also suitable for wireless applications.\",\"PeriodicalId\":446218,\"journal\":{\"name\":\"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)\",\"volume\":\"289 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIDCS47293.2020.9179897\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIDCS47293.2020.9179897","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Impact of Graded Back-Barrier on Linearity of Recessed Gate InAlN/GaN HEMT
Work presented in this paper reports the impact of graded AlGaN back-barrier on the linearity performance of lattice-matched InAlN/AlN/GaN recess gate device. Specifically, a comparison is made on the linearity of the proposed device with and without a graded back barrier layer. Various device performance matrices namely transconductance (gm) and its higher-order derivatives, second and third-order voltage intercept point (VIP2, VIP3), 3rd order input intercept point (IIP3), 3rd inter-modulation distortion (IMD3) and 1-dB compression point have been investigated and discussed for the proposed device architecture. Results obtained from TCAD simulation of the proposed device confirms that by using graded back-barrier the linearity performance matrices of the device are improved, which further shows that the proposed device is also suitable for wireless applications.