Sudipta Ghosh, S. Kundu, S. Guha, J. Ghosh, Prithviraj Pachal, S. Sarkar
{"title":"体厚对梯度沟道三金属双栅堆叠栅极TFET器件性能的影响","authors":"Sudipta Ghosh, S. Kundu, S. Guha, J. Ghosh, Prithviraj Pachal, S. Sarkar","doi":"10.1109/VLSIDCS47293.2020.9179899","DOIUrl":null,"url":null,"abstract":"In this work the authors presented a 2-D analytical drain current model of graded channel tri-metal double gate (TMDG) TFET with stacked gate-oxide structure. The parabolic approximation method with suitable boundary conditions has been applied to solve Poisson’s equation of surface potential in the channel region. Therefor the tunneling generation rate is integrated over source-channel junction area to derive the drain current expression. The proposed model demonstrates the impact of graded channel as a potential barrier at the channel region to reduce leakage current in OFF state and as well as in ON state. High doping concentration at the junction of source and channel boosts up band-to-band tunneling, which reduces subthreshold slope consequently. Proper choice of work function for the gate electrodes gives better results in terms of ION/IOFF ratio and SS. The stack gate structure provides better gate control over channel region with lesser leakage current. The explanatory aftereffects of the proposed model have been approved against the TCAD reproduction information in this work.","PeriodicalId":446218,"journal":{"name":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Effect of Body Thickness on Device Performance of Graded Channel Tri-Metal Double Gate Stack Gate TFET\",\"authors\":\"Sudipta Ghosh, S. Kundu, S. Guha, J. Ghosh, Prithviraj Pachal, S. Sarkar\",\"doi\":\"10.1109/VLSIDCS47293.2020.9179899\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work the authors presented a 2-D analytical drain current model of graded channel tri-metal double gate (TMDG) TFET with stacked gate-oxide structure. The parabolic approximation method with suitable boundary conditions has been applied to solve Poisson’s equation of surface potential in the channel region. Therefor the tunneling generation rate is integrated over source-channel junction area to derive the drain current expression. The proposed model demonstrates the impact of graded channel as a potential barrier at the channel region to reduce leakage current in OFF state and as well as in ON state. High doping concentration at the junction of source and channel boosts up band-to-band tunneling, which reduces subthreshold slope consequently. Proper choice of work function for the gate electrodes gives better results in terms of ION/IOFF ratio and SS. The stack gate structure provides better gate control over channel region with lesser leakage current. The explanatory aftereffects of the proposed model have been approved against the TCAD reproduction information in this work.\",\"PeriodicalId\":446218,\"journal\":{\"name\":\"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIDCS47293.2020.9179899\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIDCS47293.2020.9179899","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Effect of Body Thickness on Device Performance of Graded Channel Tri-Metal Double Gate Stack Gate TFET
In this work the authors presented a 2-D analytical drain current model of graded channel tri-metal double gate (TMDG) TFET with stacked gate-oxide structure. The parabolic approximation method with suitable boundary conditions has been applied to solve Poisson’s equation of surface potential in the channel region. Therefor the tunneling generation rate is integrated over source-channel junction area to derive the drain current expression. The proposed model demonstrates the impact of graded channel as a potential barrier at the channel region to reduce leakage current in OFF state and as well as in ON state. High doping concentration at the junction of source and channel boosts up band-to-band tunneling, which reduces subthreshold slope consequently. Proper choice of work function for the gate electrodes gives better results in terms of ION/IOFF ratio and SS. The stack gate structure provides better gate control over channel region with lesser leakage current. The explanatory aftereffects of the proposed model have been approved against the TCAD reproduction information in this work.