Design of Low power & High Performance Multi Source H-Tree Clock Distribution Network

Abstract

Power and timing optimization of Clock Distribution Networks (CDN) in lower technology nodes is a difficult challenge in the quest to develop low-power and high- performance designs. The drawbacks of conventional Clock Tree Synthesis (CTS) - high power consumption, increased latency and skew are targeted. Multi Source Clock Tree Synthesis (MSCTS) with a symmetric H-Tree is designed and implemented using 7nm technology node. Multiple clock sources in the design improves clock latency and skew significantly leading to reduction of buffers added to optimize hold timing, hence resulting in improvement of overall power dissipation along with clock QoR metrics. Compared to conventional clock distribution network, latency, skew and power consumption is improved by 28%, 13% and 32.8% respectively.