Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)最新文献_第7页

Algorithms for solving Boolean satisfiability in combinational circuits 组合电路中布尔可满足性的求解算法

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307557

L. G. Silva, L. M. Silveira, Joao Marques-Silva

{"title":"Algorithms for solving Boolean satisfiability in combinational circuits","authors":"L. G. Silva, L. M. Silveira, Joao Marques-Silva","doi":"10.1145/307418.307557","DOIUrl":"https://doi.org/10.1145/307418.307557","url":null,"abstract":"Boolean satisfiability is a ubiquitous modeling tool in Electronic Design Automation (EDA). It finds application in test pattern generation, delay-fault testing, combinational equivalence checking and circuit delay computation, among many other problems. Moreover Boolean satisfiability is in the core of algorithms for solving binate covering problems. This paper describes how Boolean satisfiability algorithms can take circuit structure into account when solving instances derived from combinational circuits. Potential advantages include smaller run times, the utilization of circuit-specific search pruning techniques, avoiding the overspecification problem that characterizes Boolean satisfiability testers, and reducing the time for iteratively generating instances of SAT from circuits. The experimental results obtained on several benchmark examples in two different problem domains display dramatic reductions in the run times of the algorithms, and provide clear evidence that computed solutions can have significantly less specified variable assignments than those obtained with common SAT algorithms.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114691265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 50

Testing in nanometer technologies 纳米技术测试

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1109/DATE.1999.761089

T. Williams

{"title":"Testing in nanometer technologies","authors":"T. Williams","doi":"10.1109/DATE.1999.761089","DOIUrl":"https://doi.org/10.1109/DATE.1999.761089","url":null,"abstract":"Summary form only given. The last 25 years has seen a dramatic increase in gate count and the Design for Testability techniques such as Full Scan, LSSD, BIST, etc. have been developed to cope with this. However, there is now a significant difference brought on by the technology developments facing us. The onset of deep sub-micron (now currently alluded to as Nanometer Technology) is changing the way chips are being designed and manufactured. Because of the large capacity of these new chips, plus the expense of new designs, embedded systems are setting the pace for today and the future. New problems are arising that are driving design automation to integrate all the tools that are needed to successfully take a design from concept to reality in this new design environment. Test is one part of this process that is getting significant attention. An area once classified as a \"back end\" process in the design flow is moving closer to the \"front end\". Design methodologies are incorporating test-related structures in the beginning of the design cycle. In addition, standards to manage the test complexity of these large designs are being proposed. For example, IEEE P1500 is working towards defining a structure for embedded cores such that tests can be delivered to these cores. This alone is a strong challenge for the Test Community. It is clear that the design and testing of embedded systems is the key challenge facing the Test Community.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134623279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A digital partial built-in self-test structure for a high performance automatic gain control circuit 一种用于高性能自动增益控制电路的数字部分内置自检结构

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307496

A. Lechner, J. Ferguson, A. Richardson, B. Hermes

引用次数: 6

Sequential circuit test generation using decision diagram models 时序电路测试用决策图模型生成

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307602

J. Raik, R. Ubar

引用次数: 20

Efficient BIST hardware insertion with low test application time for synthesized data paths 高效的BIST硬件插入，降低了合成数据路径的测试应用时间

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307507

N. Nicolici, B. Al-Hashimi

{"title":"Efficient BIST hardware insertion with low test application time for synthesized data paths","authors":"N. Nicolici, B. Al-Hashimi","doi":"10.1145/307418.307507","DOIUrl":"https://doi.org/10.1145/307418.307507","url":null,"abstract":"In this paper new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is based on concurrent testing of modules with identical physical information by sharing the test pattern generators in a partial intrusion BIST environment. Furthermore, to reduce the number of signature analysis registers and test application time the same type modules are grouped in test compatibility classes and n-input k-bit comparators are used to check the results. The test application time is computed using an incremental test scheduling approach. An existing test scheduling algorithm is modified to obtain an efficient trade-off between the algorithm complexity and testable design space exploration. A cost function based on both test application time and area overhead is defined and a tabu search-based heuristic capable of exploring the solution space in a very rapid time is presented. To reduce the computational time testable design space exploration is carried our in two phases: test application time reduction phase and BIST area reduction phase. Experimental results are included confirming the efficiency of the proposed methodology.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121987193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Automotive electronics-a challenge for systems engineering 汽车电子——对系统工程的挑战

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307425

Peter Thoma

{"title":"Automotive electronics-a challenge for systems engineering","authors":"Peter Thoma","doi":"10.1145/307418.307425","DOIUrl":"https://doi.org/10.1145/307418.307425","url":null,"abstract":"Abstract only given, as follows. The increasing demand for dynamically controlled safety features, driving comfort and operational convenience in upper class cars require an intensive use of ECUs (electronic control units) including software. A network of up to 70 ECUs which are communicating via buses is mandatory for the required functionality. On the one hand, complexity of ECUs is rapidly increasing and time to market is decreasing. On the other hand, automotive electronics is developed together with many suppliers under control of the OEMs. Furthermore, 30% of the value added in automotives is up to electronics. Thus, from a technical, an administrative and from a business point of view the car manufacturers have a vital interest to improve and shorten the software development process for ECUs together with all partners involved. As a consequence, a general objective is to improve the ECU development process based on standards. Besides OSEK as an already accepted standard for ECU software operating systems in Germany, the OEMs are also interested in standards for bus systems or for model exchange formats, to mention just a few. In addition, an improved ECU design process covers system analysis, system specification, system design, automatic code generation, an integration of ECUs and the corresponding software in a real environment as well as calibration and after sales services. This presentation gives an overview about the current situation in automotive electronics design, presents a new design process and discusses the challenges.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127299509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

EXPRESSION: a language for architecture exploration through compiler/simulator retargetability EXPRESSION:一种通过编译器/模拟器的可重定向性进行架构探索的语言

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307549

A. Halambi, P. Grun, Vijay Ganesh, A. Khare, N. Dutt, A. Nicolau

引用次数: 442

Battery-powered digital CMOS design 电池供电的数字CMOS设计

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307455

Massoud Pedram, Qing Wu

引用次数: 64

Codesign of embedded systems based on Java and reconfigurable hardware components 基于Java和可重构硬件组件的嵌入式系统协同设计

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307466

Josef Fleischmann, K. Buchenrieder, R. Kress

引用次数: 21

Fast, robust DC and transient fault simulation for nonlinear analogue circuits 快速，鲁棒的直流和暂态故障非线性模拟电路仿真

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307498

Z. Yang, Mark Zwolinski

引用次数: 23