Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)最新文献

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An Efficient And Flexible Methodology For Modelling And Simulation Of Heterogeneous Mechatronic Systems 一种高效灵活的异构机电系统建模与仿真方法
S. Scherber, C. Müller-Schloer
{"title":"An Efficient And Flexible Methodology For Modelling And Simulation Of Heterogeneous Mechatronic Systems","authors":"S. Scherber, C. Müller-Schloer","doi":"10.1145/307418.307513","DOIUrl":"https://doi.org/10.1145/307418.307513","url":null,"abstract":"The complexity of mechatronic systems increases continuously. The need of simulation to evaluate these systems in an early design stage is an evident fact. This paper presents a new approach for simulation of heterogeneous mechatronic systems. The aim of the development was to combine openness and flexibility with a high simulation speed and accuracy. Additionally to the description of algorithms and methods, the implementation and an example application are discussed.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"3 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131309509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-speed software-based platform for embedded software of a single-chip MPEG-2 video encoder LSI with HDTV scalability 基于高速软件的嵌入式软件平台的单片MPEG-2视频编码器LSI具有HDTV可扩展性
Katsuyuki Ochiai, Hiroe Iwasaki, J. Naganuma, M. Endo, T. Ogura
{"title":"High-speed software-based platform for embedded software of a single-chip MPEG-2 video encoder LSI with HDTV scalability","authors":"Katsuyuki Ochiai, Hiroe Iwasaki, J. Naganuma, M. Endo, T. Ogura","doi":"10.1145/307418.307510","DOIUrl":"https://doi.org/10.1145/307418.307510","url":null,"abstract":"This paper proposes a high-speed software-based platform for embedded software and evaluates its benefits on a commercial MPEG-2 video encoder LSI with HDTV scalability, The platform is written in C/C++ languages without any hardware description languages (HDLs) for high-speed simulation. This platform is applicable before writing up complete HDLs. The simulation speed is very fast and more than 600 times faster than compiled HDL simulators using RTL description. Fifty percent of the bugs in the final embedded software were located efficiently and quickly, and the design turn-around time was shortened by more than 25%. This platform provides sufficient performance and capability for validating practical embedded software.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130792865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Identification and exploitation of symmetries in DSP algorithms 识别和利用DSP算法中的对称性
C. V. Eijk, E. Jacobs, B. Mesman, A. Timmer
{"title":"Identification and exploitation of symmetries in DSP algorithms","authors":"C. V. Eijk, E. Jacobs, B. Mesman, A. Timmer","doi":"10.1145/307418.307572","DOIUrl":"https://doi.org/10.1145/307418.307572","url":null,"abstract":"In many algorithms, particularly those in the DSP domain, certain forms of symmetry can be observed. To efficiently implement such algorithms, it is often possible to exploit these symmetries. However current hardware and software compilers show deficiencies, because they cannot identify them. In this paper, we propose two techniques to automatically detect and utilize symmetry. Both techniques introduce sequence edges between operations such that the feasibility of the scheduling problem is preserved, while the symmetry is broken. In combination with existing techniques for constraint analysis, this enhances the quality of compilers considerably, as is shown by benchmark results.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130960776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Scaling deeper to submicron: on-line testing to the rescue 深入到亚微米:在线测试拯救
M. Nicolaidis, Y. Zorian
{"title":"Scaling deeper to submicron: on-line testing to the rescue","authors":"M. Nicolaidis, Y. Zorian","doi":"10.1145/307418.307539","DOIUrl":"https://doi.org/10.1145/307418.307539","url":null,"abstract":"Summary form only given. Progress in technological scaling allows the integration into a single chip of hundreds of millions of transistors, moving quickly to the multi-billion transistor capacities. Achieving acceptable quality and reliability levels for these complex products is one of the most critical issues that need to be faced. Testability is therefore a key factor that could limit these trends if not addressed adequately. At these levels of complexity external testing is becoming infeasible due to ATPG limitations. At the same time, the scan approach is losing interest due to the increasing length of scan chains (and thus test length), and low test application speed. At-speed test is a major limitation at a context where increasing clock frequencies (moving quickly to the multi-GHz domain), are making timing faults predominant. Automatic Test Equipment (ATE) is another important limitation, since, although its very high cost, it does not offer the memory capacities/depth and test application speed required for testing present day ICs. Under these constraints, the only realistic issue is to extend the BIST practice beyond memory testing. This requires new developments on logic BIST for increasing fault coverage while containing hardware cost. Furthermore, new developments on fault modeling, fault simulation, and ATPG tools are needed to encounter for timing faults, cross talk, ground bounce and other spurious faults. These developments should be oriented towards a BIST approach.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130991795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Kernel scheduling in reconfigurable computing 可重构计算中的内核调度
R. Maestre, F. Kurdahi, N. Bagherzadeh, H. Singh, R. Hermida, Milagros Fernández
{"title":"Kernel scheduling in reconfigurable computing","authors":"R. Maestre, F. Kurdahi, N. Bagherzadeh, H. Singh, R. Hermida, Milagros Fernández","doi":"10.1145/307418.307460","DOIUrl":"https://doi.org/10.1145/307418.307460","url":null,"abstract":"Reconfigurable computing is a flexible way of facing with a single device a wide range of applications with a good level of performance. This area of computing involves different issues and concepts when compared with conventional computing systems. One of these concepts is context lending. The context refers to the coded configuration information to implement a particular circuit behaviour. An important problem for reconfigurable computing is the scheduling of a group of kernels (sub-tasks) that constitute a complex application for minimum execution time. In this paper, we show how the different execution orders for these sub-tasks may result in varying levels of performance. We formulate an analytical approach and present a solution for this new problem through this work.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132352835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 52
OTA amplifiers design on digital sea-of-transistors array 基于数字晶体管海阵列的OTA放大器设计
JungBum Choi, S. Bampi
{"title":"OTA amplifiers design on digital sea-of-transistors array","authors":"JungBum Choi, S. Bampi","doi":"10.1145/307418.307500","DOIUrl":"https://doi.org/10.1145/307418.307500","url":null,"abstract":"This paper presents measurement results of OTA (Operational Transconductance Amplifiers) designed in 1.0 /spl mu/m CMOS digital technology implemented in two different methodologies: in a fixed-size transistors array and in a full-custom design. Some characteristic parameters of OTA'S are compared with HSPICE simulations.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"261 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132362865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A method to diagnose faults in linear analog circuits using an adaptive tester 利用自适应测试仪诊断线性模拟电路故障的方法
É. Cota, L. Carro, M. Lubaszewski
{"title":"A method to diagnose faults in linear analog circuits using an adaptive tester","authors":"É. Cota, L. Carro, M. Lubaszewski","doi":"10.1145/307418.307487","DOIUrl":"https://doi.org/10.1145/307418.307487","url":null,"abstract":"This work presents a new diagnosis method for use in an adaptive analog tester. The tester is able to detect faults in any linear circuit by learning a reference behaviour in a first step, and comparing this behaviour against the output of the circuit under test in a second step. Considering the same basic structure, the diagnosis method consists on injecting probable faults in a mathematical model of the circuit and later comparing its output with the output of the real faulty circuit. This method has been successfully applied to a case study, a biquad filter. Component soft, large, and hard deviations, and faults in operational amplifiers were considered. The results obtained from practical experiments with this analog circuit are discussed in the paper.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131344963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Minimal length diagnostic tests for analog circuits using test history 使用测试历史的模拟电路的最小长度诊断测试
A. Gomes, A. Chatterjee
{"title":"Minimal length diagnostic tests for analog circuits using test history","authors":"A. Gomes, A. Chatterjee","doi":"10.1145/307418.307488","DOIUrl":"https://doi.org/10.1145/307418.307488","url":null,"abstract":"In this paper we propose an efficient transient test generation method to comprehensively test analog circuits using minimum test time. A divide and conquer strategy is formulated to sequentially synthesize the test stimulus for the entire duration of test. We use a novel measurement procedure to resolve ambiguities in the present measurement sample by using class association information from the previous samples. This sequential formulation of test generation problem enables fault dropping and greatly reduces simulation and optimization effort. Additionally, this method is immune to noise and tests can be easily calibrated for use in hardware testers.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114964993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Efficient switching activity simulation under a real delay model using a bitparallel approach 用位并行方法模拟真实延迟模型下的高效开关活动
Markus Bühler, M. Papesch, K. Kapp, U. Baitinger
{"title":"Efficient switching activity simulation under a real delay model using a bitparallel approach","authors":"Markus Bühler, M. Papesch, K. Kapp, U. Baitinger","doi":"10.1145/307418.307544","DOIUrl":"https://doi.org/10.1145/307418.307544","url":null,"abstract":"Estimating switching activity is a crucial step in optimizing circuits for low power. In this paper, a fast gate level switching activity estimator for combinational circuits is presented. The combination of event driven and bitparallel simulation allows for high accuracy due to the real delay model of the former while maintaining the speedup of the latter. This is demonstrated by detailed experimental results.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114433914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A fault list reduction approach for efficient bridge fault diagnosis 基于故障列表简化的桥梁故障诊断方法
Jue Wu, G. S. Greenstein, E. Rudnick
{"title":"A fault list reduction approach for efficient bridge fault diagnosis","authors":"Jue Wu, G. S. Greenstein, E. Rudnick","doi":"10.1145/307418.307508","DOIUrl":"https://doi.org/10.1145/307418.307508","url":null,"abstract":"A new fault list reduction approach is proposed for use in the first stage of a two-stage bridge fault diagnosis procedure. Modified structural analysis and layout extraction procedures are performed to obtain a reduced realistic bridge fault list that can be used in the second stage, which employs diagnostic fault simulation. The fault list reduction approach can reduce the final candidate bridge fault list by 92% to 99% compared with the diagnosis results achieved by the diagnostic fault simulator alone.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114598343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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