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Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)最新文献

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Virtual Socket Interface Alliance 虚拟套接字接口联盟
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-03-09 DOI: 10.1109/DATE.1999.761118
Ralf Seepold
{"title":"Virtual Socket Interface Alliance","authors":"Ralf Seepold","doi":"10.1109/DATE.1999.761118","DOIUrl":"https://doi.org/10.1109/DATE.1999.761118","url":null,"abstract":"1 VSI Builds Momentum to Solve Design Reuse Imperative (Larry Rosenberg, Chair, VSI Technical Committee, USA) For over twenty years now, alarmists have been warning the electronics industry of an emerging “design productivity gap”. This is based on the exponential growth of silicon implementation capacity which grows at a compound annual growth rate of over 58% per year. This should be compared to the most optimistic projection for productivity growth, which is around 23% per year. Hence, there should have been an exponentially growing gap between what silicon can hold and what designers can define into the silicon. This tutorial will explain in detail how the semiconductor/EDA industries have coped with this problem up to now and why the techniques that have served us so well for over 30 years, will no longer work in the future. In addition, silicon capacity finally has reached the point where true product convergence can occur i.e. complete designs comprising disparate technical domains can be merged onto a single System-Chip (SoC). The solution to both the “design productivity gap” and the “convergence challenge” can both solved by design reuse of Virtual Components. This is the vision on which the VSI Alliance was created.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"48 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114029403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 70
Exploring the combination of I/sub DDQ/ and i/sub DDt/ testing: energy testing 探索I/sub DDQ/与I/sub DDt/检测的结合:能量检测
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-03-09 DOI: 10.1109/DATE.1999.761180
J. Rius, J. Figueras
{"title":"Exploring the combination of I/sub DDQ/ and i/sub DDt/ testing: energy testing","authors":"J. Rius, J. Figueras","doi":"10.1109/DATE.1999.761180","DOIUrl":"https://doi.org/10.1109/DATE.1999.761180","url":null,"abstract":"The feasibility of combining I/sub DDQ/ and and i/sub DDt/ testing to detect defective CMOS circuits by measuring the energy consumed by the tested circuit is considered. The energy chronogram of a circuit is used as an energy signature which makes it possible to distinguish between defect-free and defective circuits. Exploratory implementation of the proposed method is presented and experimental results obtained from in-house full custom circuits and commercially available circuits are discussed.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124857912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Influence of caching and encoding on power dissipation of system-level buses for embedded systems 缓存和编码对嵌入式系统系统级总线功耗的影响
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307458
W. Fornaciari, D. Sciuto, C. Silvano
{"title":"Influence of caching and encoding on power dissipation of system-level buses for embedded systems","authors":"W. Fornaciari, D. Sciuto, C. Silvano","doi":"10.1145/307418.307458","DOIUrl":"https://doi.org/10.1145/307418.307458","url":null,"abstract":"This paper proposes a methodology to evaluate the effects of encodings on the power consumption of system-level buses in the presence of multi-level cache memories. The proposed model can consider any cache configuration in terms of size, associativity and block. It includes also the most widely adopted power oriented encoding techniques for data and address buses. Experimental results show how the proposed model can be effectively adopted to configure the memory hierarchy and the system bus architecture from the power point of view.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127290367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Symbolic reachability analysis of large finite state machines using don't cares 使用don't cares对大型有限状态机进行符号可达性分析
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307430
Youpyo Hong, P. Beerel
{"title":"Symbolic reachability analysis of large finite state machines using don't cares","authors":"Youpyo Hong, P. Beerel","doi":"10.1145/307418.307430","DOIUrl":"https://doi.org/10.1145/307418.307430","url":null,"abstract":"Reachability analysis of finite state machines is essential to many computer-aided design applications. We present new techniques to improve both approximate and exact reachability analysis using don't cares. First, we propose an iterative approximate reachability analysis technique in which don't care sets derived from previous iterations are used in subsequent iterations for better approximation. Second, we propose new techniques to use the final approximation to enhance the capability and efficiency of exact reachability analysis. Experimental results show that the new techniques can improve reachability analysis significantly.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116119653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Computing timed transition relations for sequential cycle-based simulation 时序循环仿真中时序转换关系的计算
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1109/DATE.1999.761090
G. Cabodi, P. Camurati, C. Passerone, S. Quer
{"title":"Computing timed transition relations for sequential cycle-based simulation","authors":"G. Cabodi, P. Camurati, C. Passerone, S. Quer","doi":"10.1109/DATE.1999.761090","DOIUrl":"https://doi.org/10.1109/DATE.1999.761090","url":null,"abstract":"In this paper we address the problem of computing silent paths in an Finite State Machine (FSM). These paths are characterized by no observable activity under constant inputs, and can be used for a variety of applications, from verification, to synthesis, to simulation. First, we describe a new approach to compute the Timed Transition Relation of an FSM. Then, we concentrate on applying the methodology to simulation of reactive behaviours. In this field, we automatically extract a BDD-based behavioral model from the RT or gate level description. The behavioral model as able to \"jump\" in time and to avoid the simulation of internal events. Finally, we discuss a set of promising experimental results in a simulation environment under the Ptolemy simulator.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122999466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An object-based executable model for simulation of real-time Hw/Sw systems 一种基于对象的可执行模型，用于实时软硬件系统的仿真
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307512
O. Pasquier, J. P. Calvez
{"title":"An object-based executable model for simulation of real-time Hw/Sw systems","authors":"O. Pasquier, J. P. Calvez","doi":"10.1145/307418.307512","DOIUrl":"https://doi.org/10.1145/307418.307512","url":null,"abstract":"This paper describes a simulation technique for real-time Hw/Sw systems based on an object executable model. It allows designers to seamlessly estimate and verify their solutions from a high-level functional description to a Hw/Sw partitioned design. The same model, enhanced with algorithms, can be used to simulate interpreted models in order to observe the behavior of a whole system and its environment, as well as uninterpreted models which are useful for performance estimation and so help Hw/Sw partitioning. Our (co-)simulation technique is based on the translation of a high level model of the application into a C++ program which uses a library of predefined classes. While running, the program produces an event trace, the contents of which can be set by the user. This technique allows us to quickly analyze the influence of application or architecture parameters on the application behavior.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114262901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A physical design tool for built-in self-repairable static RAMs 一个用于内置自修复静态ram的物理设计工具
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307594
K. Chakraborty, Anurag P. Gupta, M. Bhattacharya, S. Kulkarni, P. Mazumder
{"title":"A physical design tool for built-in self-repairable static RAMs","authors":"K. Chakraborty, Anurag P. Gupta, M. Bhattacharya, S. Kulkarni, P. Mazumder","doi":"10.1145/307418.307594","DOIUrl":"https://doi.org/10.1145/307418.307594","url":null,"abstract":"A novel physical design tool, BISRAMGEN, that generates layout geometries of parametrized built-in self-repairable SRAM modules, producing significant improvement in testability, reliability, production yield and manufacturing cost of ASICs and microprocessors with embedded RAMs, is presented.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114412271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Systematic biasing of negative feedback amplifiers 负反馈放大器的系统偏置
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307515
C. Verhoeven, A. V. Staveren
{"title":"Systematic biasing of negative feedback amplifiers","authors":"C. Verhoeven, A. V. Staveren","doi":"10.1145/307418.307515","DOIUrl":"https://doi.org/10.1145/307418.307515","url":null,"abstract":"A biasing method is described intended to make automated biasing of at least some classes of analog circuits straightforward. It has been tested for linear amplifiers, though it is not restricted to that class. A systematic way to introduce bias sources in a circuit is discussed. Also methods for reducing the number of bias sources and bias feedback loops are given. Application of the method has shown that at least for the class of amplifiers the theory is well suited for automation.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123956854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
The Rugby Model: a conceptual frame for the study of modelling, analysis and synthesis concepts of electronic systems 拉格比模型:研究电子系统建模、分析和综合概念的概念框架
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307501
A. Jantsch, Shashi Kumar, A. Hemani
{"title":"The Rugby Model: a conceptual frame for the study of modelling, analysis and synthesis concepts of electronic systems","authors":"A. Jantsch, Shashi Kumar, A. Hemani","doi":"10.1145/307418.307501","DOIUrl":"https://doi.org/10.1145/307418.307501","url":null,"abstract":"We propose a conceptual framework, called the Rugby Model, in which designs, design processes and design tools can be studied. It is an extension of the Y chart and adds two dimensions for design representation, namely Data and Tune. The behavioural domain of Y chart is replaced by a more restricted domain called Computation. The structural and physical domains of Y chart are merged into a more general domain called Communication. A fifth dimension deals with design manipulations and transformations at three abstraction levels. The model shall establish a common understanding of modelling and design process concepts for communication and education in the community. In a case study we illustrate how a design can be characterized with the concepts the Rugby model.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121580372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Logic transformation for low power synthesis 低功率合成的逻辑变换
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1109/DATE.1999.761112
Ki-Wook Kim, Ting-Ting Hwang, C.L. Liu, S. Kang
{"title":"Logic transformation for low power synthesis","authors":"Ki-Wook Kim, Ting-Ting Hwang, C.L. Liu, S. Kang","doi":"10.1109/DATE.1999.761112","DOIUrl":"https://doi.org/10.1109/DATE.1999.761112","url":null,"abstract":"In this paper we present a new approach to the problem of local logic transformation for reduction of power dissipation in logic circuits. Based on the finite-state input transition (FIT) power dissipation model, we introduce a cost function which accounts for the effects of input capacitance, input slew rate, internal parasitic capacitance of logic gates, interconnect capacitance, as well as switching power. Our approach provides an efficient way of estimating estimating the global effect of local logic transformations in logic circuits. In our approach, the FIT model for the transitive fanout cells of a locally transformed subcircuit can be reused to measure the global power dissipation by varying the input probabilities of the transitive fanout cells. Local logic transformation is carried our based on compatible sets of permissible functions (CSPF). Experimental results show that local logic transformation based on CSPF using our cost function can reduce power consumption by about 36% on average without increase in the worst-case circuit delay.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126301294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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