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Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)最新文献

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An effective BIST architecture for fast multiplier cores 快速乘法器核心的有效BIST架构
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307469
A. Paschalis, N. Kranitis, M. Psarakis, D. Gizopoulos, Y. Zorian
{"title":"An effective BIST architecture for fast multiplier cores","authors":"A. Paschalis, N. Kranitis, M. Psarakis, D. Gizopoulos, Y. Zorian","doi":"10.1145/307418.307469","DOIUrl":"https://doi.org/10.1145/307418.307469","url":null,"abstract":"Wallace free summation in conjunction with Booth encoding are well known techniques to design fast multiplier cores widely used as embedded cores in the design of complex systems on chip. Testing of such multiplier cores deeply embedded in complex ICs requires the utilization of a BIST architecture that can be easily synthesized along with the multiplier by the module generator. In this paper we introduce an effective BIST architecture for fast multipliers that completely complies with this requirement. The algorithmic BIST patterns that this architecture generates guarantee a fault coverage higher than 99%. The required test pattern generator consists of a simple fixed-size binary counter, independent of the multiplier size. Accumulator-based compaction is adopted since multipliers and adders co-exist in most datapath architectures.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133164379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
On programmable memory built-in self test architectures 关于可编程存储器的内置自检架构
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307593
K. Zarrineh, S. Upadhyaya
{"title":"On programmable memory built-in self test architectures","authors":"K. Zarrineh, S. Upadhyaya","doi":"10.1145/307418.307593","DOIUrl":"https://doi.org/10.1145/307418.307593","url":null,"abstract":"The design and architectures of a microcode-based memory BIST and programmable FSM-based memory BIST unit are presented. The proposed microcode-based memory BIST unit is more efficient and flexible than existing architectures. Test logic overhead of the proposed programmable versus nonprogrammable memory BIST architectures is evaluated. The proposed programmable memory BIST architectures could be used to test memories in different stages of their fabrication and therefore result in lower overall memory test logic overhead. We show that the proposed microcode-based memory BIST architecture has better extendibility and flexibility while having less test logic overhead than the programmable PSM-based memory BIST architecture.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125101569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 93
Defect-oriented mixed-level fault simulation of digital systems-on-a-chip using HDL 基于HDL的数字片上系统面向缺陷的混合级故障仿真
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307562
Marcelino B. Santos, João Paulo Teixeira
{"title":"Defect-oriented mixed-level fault simulation of digital systems-on-a-chip using HDL","authors":"Marcelino B. Santos, João Paulo Teixeira","doi":"10.1145/307418.307562","DOIUrl":"https://doi.org/10.1145/307418.307562","url":null,"abstract":"The validation of high-quality tests requires Defect-Oriented (DO) fault simulation. The purpose of this paper is to propose a methodology for mixed-level DO fault simulation, using HDL. A novel tool, veriDOFS, is introduced. Structural zooming is performed only for the system module in which the faults are injected. Verilog models for bridging and line open defects are proposed for intra-gate and inter-gate faults. Design hierarchy is exploited by pre-computing a test view of each cell in a library. The good trade-off accuracy/tractability, as well as the computational efficiency of the new tool are demonstrated by means of structural benchmarks up to 100,000 transistors and 300,000 realistic faults.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125117358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
On-chip transient current monitor for testing of low-voltage CMOS IC 片上暂态电流监测器，用于测试低压CMOS集成电路
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307560
V. Stopjaková, H. Manhaeve, M. Sidiropulos
{"title":"On-chip transient current monitor for testing of low-voltage CMOS IC","authors":"V. Stopjaková, H. Manhaeve, M. Sidiropulos","doi":"10.1145/307418.307560","DOIUrl":"https://doi.org/10.1145/307418.307560","url":null,"abstract":"In this paper, on-chip test circuitry performing the transient supply current measurement is presented. The introduced principle makes uses of the parasitic resistance of the supply connection to sense the dynamic supply current. Thus, the monitor does not cause any additional power supply voltage degradation and provides detection capabilities for open defects that usually cause a significant reduction of the I/sub DDT/ current. The proposed monitor does not affect the performance of the CUT and can be efficiently used to test low-voltage CMOS circuits. Significant results summarising possibilities and limitations of the circuit are discussed as well. The design has been implemented together with an experimental CMOS circuit using Alcatel-Mietec 0.7 /spl mu/m CMOS technology and its processing is in progress. Evaluation results of the prototype test chips are presented.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"211 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126095067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
MOCSYN: multiobjective core-based single-chip system synthesis MOCSYN:基于多目标核心的单片机系统综合
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307502
R. Dick, N. Jha
{"title":"MOCSYN: multiobjective core-based single-chip system synthesis","authors":"R. Dick, N. Jha","doi":"10.1145/307418.307502","DOIUrl":"https://doi.org/10.1145/307418.307502","url":null,"abstract":"In this paper we present a system synthesis algorithm, called MOCSYN, which partitions and schedules embedded system specifications to intellectual property cores in an integrated circuit. Given a system specification consisting of multiple periodic task graphs as well as a database of core and integrated circuit characteristics, MOCSYN synthesizes real-time heterogeneous single-chip hardware software architectures using an adaptive multiobjective genetic algorithm that is designed to escape local minima. The use of multiobjective optimization allows a single system synthesis run to produce multiple designs which trade off different architectural features. Integrated circuit price, power consumption, and area are optimized under hard real-time constraints. MOCSYN differs from previous work by considering problems unique to single-chip systems. It solves the problem of providing clock signals to cores composing a system-on-a-chip. It produces a bus structure which balances ease of layout with the reduction of bus contention. In addition, it carries out floorplan block placement within its inner loop allowing accurate estimation of global communication delays and power consumption.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115824472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 93
A new parameterizable power macro-model for datapath components 一种新的数据路径组件可参数化功率宏模型
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307434
Gerd von Cölln, L. Kruse, E. Schmidt, W. Nebel
{"title":"A new parameterizable power macro-model for datapath components","authors":"Gerd von Cölln, L. Kruse, E. Schmidt, W. Nebel","doi":"10.1145/307418.307434","DOIUrl":"https://doi.org/10.1145/307418.307434","url":null,"abstract":"We propose a novel power macro-model which is based on the Hamming-distance of two consecutive input vectors and additional information on the module structure. The model is parameterizable in terms of input bit-widths and can be applied to a wide variety of datapath components. The good trade-off between estimation accuracy, model complexity and flexibility makes the model attractive for power analysis and optimization tasks on a high level of abstraction. Furthermore, a new approach is presented, that allows one to calculate the average Hamming-distance distribution of an input data stream. It is demonstrated, that the application of Hamming-distance distributions, instead of only average values, improves the estimation accuracy for a number of typical DSP-modules and data streams.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"35 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116426013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
Formally verified redundancy removal 正式验证的冗余删除
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307479
S. Hendricx, L. Claesen
{"title":"Formally verified redundancy removal","authors":"S. Hendricx, L. Claesen","doi":"10.1145/307418.307479","DOIUrl":"https://doi.org/10.1145/307418.307479","url":null,"abstract":"In general, logic redundancy tends to degrade design-quality by introducing additional delays in signal propagation, by increasing the gate count or simply by making the resulting hardware untestable. Since they cannot always be avoided, unwanted redundancies have to be first identified and then removed from our designs. In this paper an alternative methodology to identify and remove redundancy is proposed, which is based on a formal, symbolic verification strategy. The formal framework underlying our approach aids in identifying redundancies and allows us to guarantee the correctness of their removal.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128730689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A VHDL-AMS compiler and architecture generator for behavioral synthesis of analog systems 模拟系统行为综合的VHDL-AMS编译器和体系结构生成器
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307518
A. Doboli, R. Vemuri
{"title":"A VHDL-AMS compiler and architecture generator for behavioral synthesis of analog systems","authors":"A. Doboli, R. Vemuri","doi":"10.1145/307418.307518","DOIUrl":"https://doi.org/10.1145/307418.307518","url":null,"abstract":"This paper presents a complete method for automatically translating VHDL-AMS behavioral-specifications of analog systems into op amp level net-lists of library components. We discuss the three fundamental aspects, that pertain to any behavioral synthesis environment the specification language, the rules for compiling language constructs into a technology-independent, intermediate representation, and the synthesis (mapping) of representations to net-lists (topologies) of library components, so that performance constraints are satisfied. We motivate the effectiveness of the method by presenting our synthesis results for 5 examples.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125352484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
ADOLT-An ADaptable On-Line Testing scheme for VLSI circuits adolt -一种适用于VLSI电路的在线测试方案
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307473
A. Maamar, G. Russell
{"title":"ADOLT-An ADaptable On-Line Testing scheme for VLSI circuits","authors":"A. Maamar, G. Russell","doi":"10.1145/307418.307473","DOIUrl":"https://doi.org/10.1145/307418.307473","url":null,"abstract":"ADOLT permits the error detection capabilities of a CED scheme to be adapted to the error detection requirements of an application. This reduces the impact of the scheme on the design in terms of area overheads and the effect on performance. The scheme uses a slightly modified version of Dong's code [1982] and gives a more efficient implementation than previous methods.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122955118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design methodology for IP providers IP提供商的设计方法
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307599
Jürgen Haase
{"title":"Design methodology for IP providers","authors":"Jürgen Haase","doi":"10.1145/307418.307599","DOIUrl":"https://doi.org/10.1145/307418.307599","url":null,"abstract":"Based on their experience in the IP business including a large library of DesignObjects/sup TM/ (Virtual Components) and lots of design-ins world-wide, SICAN has developed a design methodology for production of Virtual Components. This methodology includes appropriate design-flows for the IP-development as well as prerequisites and methods for successful application in customers' projects. This production flow will be completed by approaches for evaluation.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126427251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
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