Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)最新文献_第9页

Specification and validation of distributed IP-based designs with JavaCAD 使用JavaCAD规范和验证基于ip的分布式设计

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307588

M. Dalpasso, A. Bogliolo, L. Benini

引用次数: 29

The heterogeneous structure problem in hardware/software codesign: a macroscopic approach 硬件/软件协同设计中的异构结构问题:宏观方法

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307464

J. A. Maestro, D. Mozos, R. Hermida

引用次数: 2

An efficient reuse system for digital circuit design 数字电路设计的高效复用系统

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307444

A. Reutter, W. Rosenstiel

引用次数: 21

Glitch power minimization by gate freezing 通过栅极冻结使故障功率最小化

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307481

L. Benini, G. Micheli, A. Macii, E. Macii, M. Poncino, R. Scarsi

引用次数: 11

OpenJ: an extensible system level design language OpenJ:一个可扩展的系统级设计语言

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307547

Jianwen Zhu, D. Gajski

{"title":"OpenJ: an extensible system level design language","authors":"Jianwen Zhu, D. Gajski","doi":"10.1145/307418.307547","DOIUrl":"https://doi.org/10.1145/307418.307547","url":null,"abstract":"There is an increasing research interest in system level design languages which can carry designers from specification to implementation of a system-on-a-chip. Unfortunately two of the most important goals in designing such a language, are at odds with each other: heterogeneity requires components of the system to be captured precisely by domain specific models to simplify analysis and synthesis; simplicity requires a consistent notation to avoid confusion. In this paper, we focus on our effort in resolving this dilemma in an extensible language called OpenJ. In contrast to the conventional monolithic languages, OpenJ has a layered structure consisting of the kernel layer which is essentially an object oriented language designed to be simple, modular and polymorphic; the open layer which exports parameterizable language constructs; the domain layer which precisely captures the computational models essential for embedded systems. The domain layer can be provided by vendors via a common protocol defined by an open layer which enables the supersetting or/and subsetting of the kernel. A compiler has been built for this language and experiments are conducted for popular models such as synchronous, discrete event and dataflow.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128633539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Emulation of a fast reactive embedded system using a real time operating system 基于实时操作系统的快速响应嵌入式系统仿真

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307463

K. Weiß, Thorsten Steckstor, W. Rosenstiel

引用次数: 2

C for system level design C为系统级设计

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307528

G. Arnout

{"title":"C for system level design","authors":"G. Arnout","doi":"10.1145/307418.307528","DOIUrl":"https://doi.org/10.1145/307418.307528","url":null,"abstract":"Few people disagree with the fact that today about 80% of a system is software running on a \"platform\" of general purpose or custom processors (CPU and/or DSP) tightly coupled with unique dedicated hardware. This makes C (or C++) an obvious candidate for a system level design language. Without good hardware/software partitioning tools and support for C-based hardware design, the software content may have to increase by necessity. With the right hardware support a system team has the flexibility to make cost, performance, power trade-offs and decide later in the game how much of the system is software and how much is hardware. Another issue is legacy software and hardware. Legacy C software is well understood but legacy hardware is usually only available as RTL (Verilog or VHDL) at best. Therefore the ideal system level design language is C (or C++) based, accommodates hardware design but also co-exists with the vast legacy of Verilog and VHDL based re-usable hardware. CoWare N2C is practical solution, used in real life design around the world, that a) preserves the C software development paradigm for software people, b) adds the necessary clocking to C to enable hardware designers to move C functionality into a hardware architecture, and c) co-exists C for co-design and co-simulation) with existing hardware in Verilog or VHDL.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"248 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125406167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 26

A methodology and design environment for DSP ASIC fixed point refinement 一种DSP专用集成电路定点细化的方法和设计环境

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307503

R. Cmar, L. Rijnders, P. Schaumont, S. Vernalde, I. Bolsens

引用次数: 133

Interpretable symbolic small-signal characterization of large analog circuits using determinant decision diagrams 使用行列式决策图的大型模拟电路的可解释符号小信号特性

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307543

S. Tan, C. Shi

引用次数: 11

Path delay fault testing of ICs with embedded intellectual property blocks 嵌入式知识产权模块集成电路的路径延迟故障测试

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307468

D. Nikolos, H. T. Vergos, T. Haniotakis, Y. Tsiatouhas

引用次数: 6