通过栅极冻结使故障功率最小化

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI:10.1145/307418.307481

L. Benini, G. Micheli, A. Macii, E. Macii, M. Poncino, R. Scarsi

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引用次数: 11

摘要

本文提出了一种组合电路中小故障功率最小化的技术。通过将现有的一些门替换为功能相当的门(称为f门)，可以通过断言控制信号来“冻结”，从而减少了故障的总数。一个冻结门不能传播小故障到它的输出。该方法的一个重要特征是可以直接就地应用于布局级描述;因此，它保证了非常可预测的结果，并最大限度地减少了转换对电路尺寸和速度的影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Glitch power minimization by gate freezing

This paper presents a technique for glitch power minimization in combinational circuits. The total number of glitches is reduced by replacing some existing gates with functionally equivalent ones (called F-gates) that can be "frozen" by asserting a control signal. A frozen gate cannot propagate glitches to its output. An important feature of the proposed method is that it can be applied in-place directly to layout-level descriptions; therefore, it guarantees very predictable results and minimizes the impact of the transformation on circuit size and speed.

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Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)

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