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Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)最新文献

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On reducing transitions through data modifications 通过数据修改来减少转换
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307457
R. Murgai, M. Fujita
{"title":"On reducing transitions through data modifications","authors":"R. Murgai, M. Fujita","doi":"10.1145/307418.307457","DOIUrl":"https://doi.org/10.1145/307418.307457","url":null,"abstract":"Since busses take up a significant fraction of chip-area, the bus capacitances are often considerable, and the bus power may account for as much as 40% of the total power consumed on the chip. In applications where the integrity of data is not very important, data may be changed by 3 to 5% without losing too much information. One such application is that of a binary-encoded image, in which case the human eye cannot perceive the small change. However, these small changes can significantly reduce the number of transitions on the data bus and thus the power/energy consumed. We address the following problem: given a sequence of n k-bit data words and an error-tolerance e% (i,e., at most e% of the data bits are permitted to change), select the bits to be modified so that the total number of transitions is minimized. We show that a greedy strategy is not always optimum. We propose a linear-time dynamic programming based algorithm that generates an optimum solution to this problem. The experimental results for randomly generated data with a uniform distribution indicate that by changing e% data bits, the transitions can be reduced, on average, by 4e%.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127898371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Minimizing sensitivity to delay variations in high-performance synchronous circuits 最小化高性能同步电路对延迟变化的灵敏度
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307581
Xun Liu, M. Papaefthymiou, E. Friedman
{"title":"Minimizing sensitivity to delay variations in high-performance synchronous circuits","authors":"Xun Liu, M. Papaefthymiou, E. Friedman","doi":"10.1145/307418.307581","DOIUrl":"https://doi.org/10.1145/307418.307581","url":null,"abstract":"This paper investigates retiming and clock skew scheduling for improving the tolerance of synchronous circuits to delay variations. It is shown that when both long and short paths are considered, circuits optimized by the combined application of the two techniques are more tolerant to delay variations than when optimized by either of the two techniques separately. A novel mixed-integer linear programming formulation is given for simultaneous retiming and clock scheduling with a target clock period and tolerance under setup and hold constraints. Experiments with LGSynth93 and ISCAS89 benchmark circuits demonstrate the effectiveness of the combined optimization. For half of the test circuits, tolerance to delay variations increased by at least 23% over the separate application of retiming and clock scheduling. Moreover, for two thirds of the test circuits, maximum tolerance improved by at least 11%.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132511051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Hierarchical constraint transformation using directed interval search for analog system synthesis 基于有向区间搜索的分层约束变换模拟系统综合
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307517
N. Dhanwada, A. Núñez-Aldana, R. Vemuri
{"title":"Hierarchical constraint transformation using directed interval search for analog system synthesis","authors":"N. Dhanwada, A. Núñez-Aldana, R. Vemuri","doi":"10.1145/307418.307517","DOIUrl":"https://doi.org/10.1145/307418.307517","url":null,"abstract":"In this paper, we present a hierarchical approach for constraint transformation. The important features of this are: a genetic algorithm (GA) based search engine that computes design parameter ranges, a hierarchically organized characterization mechanism based on the concept of directed intervals that assists the search engine and an analog performance estimator. Experiments were conducted comparing the hierarchical approach with a flat bottom-up one. The results obtained demonstrate the effectiveness of the former approach. Experimental results highlighting the impact of using the characterization information within the constraint transformation process are also presented.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130253807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
Verifying imprecisely working arithmetic circuits 验证工作不精确的算术电路
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307451
M. Huhn, K. Schneider, T. Kropf, G. Logothetis
{"title":"Verifying imprecisely working arithmetic circuits","authors":"M. Huhn, K. Schneider, T. Kropf, G. Logothetis","doi":"10.1145/307418.307451","DOIUrl":"https://doi.org/10.1145/307418.307451","url":null,"abstract":"If real number calculations are implemented as circuits, only a limited preciseness can be obtained. Hence, formal verification cannot be used to prove the equivalence between the mathematical specification based on real numbers and the corresponding hardware realization. Instead, the number representation has to be taken into account in that certain error bounds have to be verified. For this reason, we propose formal methods to guide the complete design flow of these circuits from the highest abstraction level down to the register-transfer level with formal verification techniques that are appropriate for the corresponding level. Hence, our method is hybrid in the sense that it combines different state-of-the-art verification techniques. Using our method, we establish a more detailed notion of correctness that considers beneath the control and data flow also the preciseness of the numeric calculations. We illustrate the method with the discrete cosine transform as a real-world example.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"64 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133073239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Performance driven resynthesis by exploiting retiming-induced state register equivalence 利用时序诱导状态寄存器等效的性能驱动重合成
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307579
P. Kalla, M. Ciesielski
{"title":"Performance driven resynthesis by exploiting retiming-induced state register equivalence","authors":"P. Kalla, M. Ciesielski","doi":"10.1145/307418.307579","DOIUrl":"https://doi.org/10.1145/307418.307579","url":null,"abstract":"This paper presents a retiming and resynthesis technique for cycle-time minimization of sequential circuits with feedback (finite state machines). Operating on the delay critical paths of the circuit, we perform a set of controlled local retimings of registers across fanout stems and logic gates, followed by local node simplifications. We guide the retiming of registers across fanout stems to induce equivalence relations among them, which are exploited for subsequent logic simplification. Our technique is able to analyze correlation of logic across register boundaries during simplification. We strive to minimize the increase in number of registers without sacrificing the cycle-time performance. The results demonstrate a favourable performance/area trade-off when compared with optimally retimed circuits.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133494357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Wavefront technology mapping 波前技术映射
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307559
L. Stok, A. Sullivan, M. Iyer
{"title":"Wavefront technology mapping","authors":"L. Stok, A. Sullivan, M. Iyer","doi":"10.1145/307418.307559","DOIUrl":"https://doi.org/10.1145/307418.307559","url":null,"abstract":"The wavefront technology mapping algorithm leads to a very simple and efficient implementation that elegantly decouples pattern matching and covering but circumvents that patterns have to be stored for the entire network simultaneously. This coupled with dynamic decomposition enables trade-off of many more alternatives than in conventional mapping algorithms. The wavefront algorithm maps optimally for minimal delay on directed acyclic graphs (DAGs) when a gain based delay model is used. It is optimal with respect to the arrival times on each path in the network. A special timing mode for multi-source nets allows minimization of other (non-delay) metrics as a secondary objective while maintaining delay optimality.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133569525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
Efficient 3D modelling for extraction of interconnect capacitances in deep submicron dense layouts 深层亚微米密集布局中互连电容提取的高效三维建模
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307567
A. Toulouse, David Bernard, C. Landrault, P. Nouet
{"title":"Efficient 3D modelling for extraction of interconnect capacitances in deep submicron dense layouts","authors":"A. Toulouse, David Bernard, C. Landrault, P. Nouet","doi":"10.1145/307418.307567","DOIUrl":"https://doi.org/10.1145/307418.307567","url":null,"abstract":"This paper introduces a set of analytical formulations for 3D modelling of inter-layer capacitances. Efficiency and accuracy are both guaranteed by the process characterization approach. Analytical modelling of interconnect capacitances is then demonstrated to be an helpful alternative to lookup tables or numerical simulations.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"190 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123181671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Combining software synthesis and hardware/software interface generation to meet hard real-time constraints 结合软件合成和硬件/软件接口生成，满足硬实时约束
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307563
S. Vercauteren, J. V. D. Steen, D. Verkest
{"title":"Combining software synthesis and hardware/software interface generation to meet hard real-time constraints","authors":"S. Vercauteren, J. V. D. Steen, D. Verkest","doi":"10.1145/307418.307563","DOIUrl":"https://doi.org/10.1145/307418.307563","url":null,"abstract":"This paper presents an orchestrated combination of software synthesis and automatic hardware/software interface generation to meet hard real-time constraints. The target applications are digital communication systems, which are specified as concurrent communicating processes. The overall approach is theoretically founded and is demonstrated on an industrial strength design, with promising results.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123905174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Full scan fault coverage with partial scan 带部分扫描的全扫描故障覆盖
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307545
X. Lin, I. Pomeranz, S. Reddy
{"title":"Full scan fault coverage with partial scan","authors":"X. Lin, I. Pomeranz, S. Reddy","doi":"10.1145/307418.307545","DOIUrl":"https://doi.org/10.1145/307418.307545","url":null,"abstract":"In this paper, a test generation based partial scan selection procedure is proposed. The procedure is able to achieve the same level of fault coverage as in a full scan design by scanning only a subset of the flip-flops. New measures are used to guide the flip-flop selection during the procedure. The proposed procedure is applied to the ISCAS-89 and the ADDENDUM-93 benchmark circuits. For all the circuits, it is possible to achieve the same fault coverage as that for full scan while scanning a portion of the flip-flops.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124027553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Synthesis of controllers for full testability of integrated datapath-controller pairs 集成数据路径-控制器对的完全可测试性控制器的综合
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307505
J. Carletta, M. Nourani, C. Papachristou
{"title":"Synthesis of controllers for full testability of integrated datapath-controller pairs","authors":"J. Carletta, M. Nourani, C. Papachristou","doi":"10.1145/307418.307505","DOIUrl":"https://doi.org/10.1145/307418.307505","url":null,"abstract":"This work facilitates the testing of datapath-controller pairs in an integrated fashion, with datapath and controller tested together in a single test session. Such an approach requires less test overhead than an approach that isolates datapath and controller from each other during test. The ability to do an integrated test is especially important when testing core-based embedded systems. The key to the approach is a careful examination of the relationship between techniques for controller synthesis and the types of gate level controller faults that can occur. A method for controller synthesis is outlined that results in a fully testable controller, so that full fault coverage of the controller can be achieved without any need for isolation during test.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124654829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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