Scaling deeper to submicron: on-line testing to the rescue

Abstract

Summary form only given. Progress in technological scaling allows the integration into a single chip of hundreds of millions of transistors, moving quickly to the multi-billion transistor capacities. Achieving acceptable quality and reliability levels for these complex products is one of the most critical issues that need to be faced. Testability is therefore a key factor that could limit these trends if not addressed adequately. At these levels of complexity external testing is becoming infeasible due to ATPG limitations. At the same time, the scan approach is losing interest due to the increasing length of scan chains (and thus test length), and low test application speed. At-speed test is a major limitation at a context where increasing clock frequencies (moving quickly to the multi-GHz domain), are making timing faults predominant. Automatic Test Equipment (ATE) is another important limitation, since, although its very high cost, it does not offer the memory capacities/depth and test application speed required for testing present day ICs. Under these constraints, the only realistic issue is to extend the BIST practice beyond memory testing. This requires new developments on logic BIST for increasing fault coverage while containing hardware cost. Furthermore, new developments on fault modeling, fault simulation, and ATPG tools are needed to encounter for timing faults, cross talk, ground bounce and other spurious faults. These developments should be oriented towards a BIST approach.