Sequential circuit test generation using decision diagram models

Abstract

A novel approach to testing sequential circuits that uses multi-level decision diagram representations is introduced. The proposed algorithm consists of a combination of scanning and conformity test generation procedures. Structural faults in both, datapath and control part are targeted. High-level simplified and fast symbolic path activation strategy is combined with random local test pattern generation for functional units. The current approach has achieved high fault coverages for known sequential circuit benchmarks in a very short time.