2020 5th IEEE International Conference on Emerging Electronics (ICEE)最新文献_第8页

Novel Polymer MEMS Capacitive Hydrogen sensor with Palladium Ring on Membrane-Mass Architecture 膜-质量结构钯环聚合物MEMS电容式氢传感器

2020 5th IEEE International Conference on Emerging Electronics (ICEE) Pub Date : 2020-11-26 DOI: 10.1109/icee50728.2020.9776818

Joel Zacharias, K. H. Nikhita, V. Seena

引用次数: 1

An Accurate Inductor Model by Incorporating Negative Mutual Inductance Effect for High-Density SoC 考虑负互感效应的高密度SoC精确电感模型

2020 5th IEEE International Conference on Emerging Electronics (ICEE) Pub Date : 2020-11-26 DOI: 10.1109/icee50728.2020.9776937

S. R. Rao, Sarath Arackal, R. Sai

{"title":"An Accurate Inductor Model by Incorporating Negative Mutual Inductance Effect for High-Density SoC","authors":"S. R. Rao, Sarath Arackal, R. Sai","doi":"10.1109/icee50728.2020.9776937","DOIUrl":"https://doi.org/10.1109/icee50728.2020.9776937","url":null,"abstract":"System-on-chip (SoC) planar inductors are vital components in miniaturized IoT systems, chip-level power electronics circuits, and RF signal processing circuits. The increasing component density in today's integrated circuits constricts the flexibility of designing a distant Conducting Guard Ring (CGR) around the inductor coil, which in turn, necessitates revisiting the existing inductance calculation formulations to attain the best accuracy. In this paper, we address the effect of Negative Mutual Inductance (NMI) caused by the CGR and propose a formula that accounts for the increase in NMI for distances between $5 mumathrm{m} text{to} 100 mumathrm{m}$. NMI has been studied on our test inductor and the “proposed model” is numerically computed. The model is correlated with the HFSS simulations of DUT for various dCGR values (distance between outer most turn of the inductor and CGR) and the results when compared with the existing formulations reported in the literature, evidently display the prominent NMI effect on the effective inductance caused by the CGR. Therefore, proving that the effect of CGR cannot be overlooked for a dense circuit layout where dCGR is less than $50 mu mathrm{m}$. At distances as small as $5 mu mathrm{m}$ – a common dCGR value in today's circuits, our formulation in an error of less than 6% when compared with the best of the reported formulations that returns a 32% error. The proposed model outperforms the best of the existing models for any dCGR up to $70 mu mathrm{m}$, and thus, can be seen as an excellent and timely tool for the high-density SoC inductor designers.","PeriodicalId":436884,"journal":{"name":"2020 5th IEEE International Conference on Emerging Electronics (ICEE)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124415693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Chemically Sprayed p-type CuS Thin Film-Characterization and Feasibility Study on Junction with n-Si for the Development of Solar Cell 化学喷涂p型cu薄膜的表征及其与n-Si结的可行性研究

2020 5th IEEE International Conference on Emerging Electronics (ICEE) Pub Date : 2020-11-26 DOI: 10.1109/icee50728.2020.9777017

A. C, Visakh V. Mohan, K. Vijayakumar

{"title":"Chemically Sprayed p-type CuS Thin Film-Characterization and Feasibility Study on Junction with n-Si for the Development of Solar Cell","authors":"A. C, Visakh V. Mohan, K. Vijayakumar","doi":"10.1109/icee50728.2020.9777017","DOIUrl":"https://doi.org/10.1109/icee50728.2020.9777017","url":null,"abstract":"Metal sulphides have been subjected to extensive research due to their excellent optoelectronic properties. Among them, CuS is a p-type material with a wide band gap in the range of 1.5-2.6 eV, having applications in various fields like sensors, solar cells, photo detectors etc. As an important non-toxic, earth abundant, highly p-doped semiconductor with its metal-like electrical conductivity, CuS has attracted much attention in recent years to fabricate wide range of optical and electrical devices. Different methods have been used for the CuS thin films deposition; among them, Chemical Spray Pyrolysis (CSP) technique is a promising one, because of its simplicity, cost effectiveness and scalability for large area deposition. This paper reports the preparation and characterization of CuS thin films deposited by vacuum free chemical spray pyrolysis. The covellite CuS thin film was grown on glass substrate at 300°C using copper chloride and thiourea as precursors without the use of any complexing agent. Optical and structural characterizations of the thin films were done using, UV-Visible optical absorption, Raman spectra, X ray diffraction, Scanning Electron Microscope. The Hall measurement showed that sample has a p-type conductivity with a hole concentration of $sim 1.37times 10^{19}text{cm}^{-3}$. Further, fabrication and characterization of pCuS/n-cSi heterojunction was also done.","PeriodicalId":436884,"journal":{"name":"2020 5th IEEE International Conference on Emerging Electronics (ICEE)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126402531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Linearity Behavior of a Pocket Doped p-type Ground Plane FDSOI: Impact of Back Biasing 口袋掺杂p型地平面FDSOI的线性特性:后偏置的影响

2020 5th IEEE International Conference on Emerging Electronics (ICEE) Pub Date : 2020-11-26 DOI: 10.1109/icee50728.2020.9776790

R. Shaik, K. P. Pradhan

{"title":"Linearity Behavior of a Pocket Doped p-type Ground Plane FDSOI: Impact of Back Biasing","authors":"R. Shaik, K. P. Pradhan","doi":"10.1109/icee50728.2020.9776790","DOIUrl":"https://doi.org/10.1109/icee50728.2020.9776790","url":null,"abstract":"In this work; a FDSOI MOSFET with p type ground plane (pGP) to suppress the depletion region under BOX, pockets in source/drain sides to mitigate the impact ionization has been used for investigating linearity figure-of-merits (FOMs) under the influence of back-bias ($mathrm{V}_{B}$) for superior tuning of device performance. Linearity investigations performed at transistor level can exponentially improve the reliability of the IC. This can reduce the need for complex circuitry and area significantly without affecting the overall system reliability. The current work focuses on analysing analog FOMs for the proposed device structure under the influence $mathrm{V}_{B}$ engineering using a well calibrated industry standard TCAD tool Silvaco ATLAS. The analysis is carried out quantitatively by extracting HD2, HD3, VIP2, VIP3 and IIP3. These merits are extracted from a single tone DC transfer characteristic output of the device considering transconductance (gm) as fundamental and its higher order coefficients ($mathrm{g}_{m2}, mathrm{g}_{m3}, ldots$) as harmonics. The results from the analysis suggest an optimized linearity at the zero-crossover point $(mathrm{V}_{dc-bias})$ in the $mathrm{g}_{m3}$ plot.","PeriodicalId":436884,"journal":{"name":"2020 5th IEEE International Conference on Emerging Electronics (ICEE)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125440504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Experimental Study of the Acoustic Field of a Single-Cell Piezoelectric Micromachined Ultrasound Transducer (PMUT) 单细胞压电微机械超声换能器(PMUT)声场实验研究

2020 5th IEEE International Conference on Emerging Electronics (ICEE) Pub Date : 2020-11-26 DOI: 10.1109/icee50728.2020.9777041

Bibhas Nayak, Harshvardhan Gupta, Kaustav Roy, Anuj Ashok, Vijayendra Shastri, R. Pratap

引用次数: 9

Surface Morphology of Step Edge on MgO Single Crystal Substrate for Josephson Junction 约瑟夫森结MgO单晶衬底阶梯边缘表面形貌研究

2020 5th IEEE International Conference on Emerging Electronics (ICEE) Pub Date : 2020-11-26 DOI: 10.1109/icee50728.2020.9776727

Mamta Dahiya, S. Pal, N. Khare

引用次数: 0

Assessment of Optical Properties of Metal Assisted Chemically Etched Black Silicon Surface Morphology in Multi-crystalline Cells and Modules by Ray-tracer Simulations 用射线示踪剂模拟评价金属辅助化学蚀刻黑硅多晶电池和组件表面形貌的光学特性

2020 5th IEEE International Conference on Emerging Electronics (ICEE) Pub Date : 2020-11-26 DOI: 10.1109/icee50728.2020.9776693

Tanushree J. B. Nath, K. Sreejith, A. Kottantharayil

引用次数: 1

Effect of Different Annealing Methods on the Performance Parameters of PEDOT:PSS/n-Si Solar Cells 不同退火方法对PEDOT:PSS/n-Si太阳能电池性能参数的影响

2020 5th IEEE International Conference on Emerging Electronics (ICEE) Pub Date : 2020-11-26 DOI: 10.1109/icee50728.2020.9776719

Anil Kumar, P. Nair, A. Antony

引用次数: 1

SPICE Based Compact Modeling of Spiral Inductor and MIM Capacitor for RF Circuit Simulations 基于SPICE的螺旋电感和MIM电容的射频电路仿真紧凑建模

2020 5th IEEE International Conference on Emerging Electronics (ICEE) Pub Date : 2020-11-26 DOI: 10.1109/icee50728.2020.9777074

Sweta Agarwal, Samriddhi Raut, H. S. Jatana, Abhishek Dixit, S. Chatterjee

引用次数: 0

Heavy-ion irradiation study in SiNT FET inverter chain using 3D-TCAD simulation 基于3D-TCAD仿真的SiNT FET逆变链重离子辐照研究

2020 5th IEEE International Conference on Emerging Electronics (ICEE) Pub Date : 2020-11-26 DOI: 10.1109/icee50728.2020.9777037

G. Durga, R. Srinivasan

引用次数: 0