An Accurate Inductor Model by Incorporating Negative Mutual Inductance Effect for High-Density SoC

Abstract

System-on-chip (SoC) planar inductors are vital components in miniaturized IoT systems, chip-level power electronics circuits, and RF signal processing circuits. The increasing component density in today's integrated circuits constricts the flexibility of designing a distant Conducting Guard Ring (CGR) around the inductor coil, which in turn, necessitates revisiting the existing inductance calculation formulations to attain the best accuracy. In this paper, we address the effect of Negative Mutual Inductance (NMI) caused by the CGR and propose a formula that accounts for the increase in NMI for distances between $5\ \mu\mathrm{m}\ \text{to}\ 100\ \mu\mathrm{m}$. NMI has been studied on our test inductor and the “proposed model” is numerically computed. The model is correlated with the HFSS simulations of DUT for various dCGR values (distance between outer most turn of the inductor and CGR) and the results when compared with the existing formulations reported in the literature, evidently display the prominent NMI effect on the effective inductance caused by the CGR. Therefore, proving that the effect of CGR cannot be overlooked for a dense circuit layout where dCGR is less than $50\ \mu \mathrm{m}$. At distances as small as $5 \mu \mathrm{m}$ – a common dCGR value in today's circuits, our formulation in an error of less than 6% when compared with the best of the reported formulations that returns a 32% error. The proposed model outperforms the best of the existing models for any dCGR up to $70\ \mu \mathrm{m}$, and thus, can be seen as an excellent and timely tool for the high-density SoC inductor designers.