Linearity Behavior of a Pocket Doped p-type Ground Plane FDSOI: Impact of Back Biasing

Abstract

In this work; a FDSOI MOSFET with p type ground plane (pGP) to suppress the depletion region under BOX, pockets in source/drain sides to mitigate the impact ionization has been used for investigating linearity figure-of-merits (FOMs) under the influence of back-bias ($\mathrm{V}_{B}$) for superior tuning of device performance. Linearity investigations performed at transistor level can exponentially improve the reliability of the IC. This can reduce the need for complex circuitry and area significantly without affecting the overall system reliability. The current work focuses on analysing analog FOMs for the proposed device structure under the influence $\mathrm{V}_{B}$ engineering using a well calibrated industry standard TCAD tool Silvaco ATLAS. The analysis is carried out quantitatively by extracting HD2, HD3, VIP2, VIP3 and IIP3. These merits are extracted from a single tone DC transfer characteristic output of the device considering transconductance (gm) as fundamental and its higher order coefficients ($\mathrm{g}_{m2},\ \mathrm{g}_{m3},\ \ldots$) as harmonics. The results from the analysis suggest an optimized linearity at the zero-crossover point $(\mathrm{V}_{dc-bias})$ in the $\mathrm{g}_{m3}$ plot.