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Semiconductor Bandgap grading of Buffer layer for performance optimization of thin solar cells 半导体带隙分级缓冲层的性能优化薄太阳能电池
2020 5th IEEE International Conference on Emerging Electronics (ICEE) Pub Date : 2020-11-26 DOI: 10.1109/icee50728.2020.9776971
Prashant Kumar, B. S. Sengar, Amitesh Kumar
{"title":"Semiconductor Bandgap grading of Buffer layer for performance optimization of thin solar cells","authors":"Prashant Kumar, B. S. Sengar, Amitesh Kumar","doi":"10.1109/icee50728.2020.9776971","DOIUrl":"https://doi.org/10.1109/icee50728.2020.9776971","url":null,"abstract":"Due to the low throughput and high-cost of Si-based Photovoltaic (PV) cells, alternatives such as thin-film PV cells based on Cu2ZnSnS4 (CZTS) and Cu2Sn1-xGexS3 (CTGS) are being sought. The buffer layer is very critical as it provides band-alignment at the absorber/window layer and also reduces defects/interfacial strain. The standard buffer layer of CdS for CIGS and CZTS has a bandgap around 2.7 eV, being detrimental for the performance of PV cells, necessitating alternative buffer layers of the higher bandgap. In this work, the role of bandgap variation has been analysed for performance optimization of CZTS based PV cells using SCAPS software. This study depicts that by bandgap grading through deploying alternative buffer materials, the performance of PV cells may be upgraded.","PeriodicalId":436884,"journal":{"name":"2020 5th IEEE International Conference on Emerging Electronics (ICEE)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116355852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Generation of singular beams using electrically addressed liquid crystal spatial light modulator 利用电寻址液晶空间光调制器产生奇异光束
2020 5th IEEE International Conference on Emerging Electronics (ICEE) Pub Date : 2020-11-26 DOI: 10.1109/icee50728.2020.9776736
Praveen Kumar, N. Nishchal
{"title":"Generation of singular beams using electrically addressed liquid crystal spatial light modulator","authors":"Praveen Kumar, N. Nishchal","doi":"10.1109/icee50728.2020.9776736","DOIUrl":"https://doi.org/10.1109/icee50728.2020.9776736","url":null,"abstract":"In this paper, we demonstrate the ability of a spatial light modulator based technique of dual-phase modulation for the generation of vector-vortex beams which have non-zero radial and azimuthal indices. The generated vector-vortex beams hold both phase and polarization singularities. These beams have gained importance because of their association with the orbital angular momentum of light. They have applications in many areas of optics.","PeriodicalId":436884,"journal":{"name":"2020 5th IEEE International Conference on Emerging Electronics (ICEE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126299181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Towards the Development of Unified Models for Memristors: Charge-Flux Relationship 迈向忆阻器统一模型的发展:电荷-通量关系
2020 5th IEEE International Conference on Emerging Electronics (ICEE) Pub Date : 2020-11-26 DOI: 10.1109/icee50728.2020.9777013
A.N. Pranavi, Tejendra Dixit, K. P. Pradhan
{"title":"Towards the Development of Unified Models for Memristors: Charge-Flux Relationship","authors":"A.N. Pranavi, Tejendra Dixit, K. P. Pradhan","doi":"10.1109/icee50728.2020.9777013","DOIUrl":"https://doi.org/10.1109/icee50728.2020.9777013","url":null,"abstract":"Memristors have garnered the great attention of the scientific community due to the immense scope in memory technology and neuromorphic computing. Like any other established devices viz. transistor, LEDs, etc. modeling of memristors is needed to develop a complete understanding of the device functionality. This becomes a major asset while constructing memristive circuits more precisely. There are several models developed to represent the memristor, which helped to understand its functioning with different device control parameters like scaling and exponential factors, input voltage, frequency, etc. In this paper, some models for memristor have been demonstrated using analytical simulations.","PeriodicalId":436884,"journal":{"name":"2020 5th IEEE International Conference on Emerging Electronics (ICEE)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116852062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Electrochemical deposition and characterization of Copper Pillar Bumps — Application towards Flip chip bonding 铜柱凸点的电化学沉积和表征-在倒装芯片键合中的应用
2020 5th IEEE International Conference on Emerging Electronics (ICEE) Pub Date : 2020-11-26 DOI: 10.1109/icee50728.2020.9777005
Sampada Sameer Naik, H. Sanjeev, Megha Agrawal, Mahalakshmi S
{"title":"Electrochemical deposition and characterization of Copper Pillar Bumps — Application towards Flip chip bonding","authors":"Sampada Sameer Naik, H. Sanjeev, Megha Agrawal, Mahalakshmi S","doi":"10.1109/icee50728.2020.9777005","DOIUrl":"https://doi.org/10.1109/icee50728.2020.9777005","url":null,"abstract":"The pre-processes targeting Flip Chip Assembly of copper pillars consists of spin coating of photo resists, direct writing, development of the photo resist, electroplating. The Flip chip assembly is targeted to verify the fine pitch bonding that is practically possible. Hence a unique design consisting of different pitch dimensions and pillar diameters are designed. In order to achieve the minimum possible pitch in the flip chip bonding, various experiments with the pre-processes viz., spin coating with different resists, direct pattern writing with different laser powers and other parameters, electroplating of copper (Cu) with varying parameters, are conducted to see the effect of each of these processes in practically achieving successful flip chip bonding/assembly with minimum pitch and minimum diameter design. This paper describes Copper pillar deposition using acid copper electrolyte by electro chemical deposition. A positive photo-resist AZ9260 up to thickness of $16 mumathrm{m}$ and smallest feature of diameter $10mumathrm{m}$ were fabricated by multi step spin coating. Spin coating and lithography parameters were optimized. Electroplating of copper pillars was carried out by pulse plating and pulse reverse technique. The deposited copper pillars were characterized by Con-focal microscopy, X-Ray Diffraction and Scanning Electron Microscopy. Electrical characterization of Copper Pillars was done by four probe method. The targeted gap (between two pillars) dimensions are $10mumathrm{m}, 20mumathrm{m}, 30mumathrm{m}$ and $40mumathrm{m}$ with the diameter dimensions of $10mumathrm{m}, 15mumathrm{m}, 20mumathrm{m}$ and $25mumathrm{m}$.","PeriodicalId":436884,"journal":{"name":"2020 5th IEEE International Conference on Emerging Electronics (ICEE)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131740965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effect of Actuation electrode design on RF Performance of RF MEMS shunt switch 驱动电极设计对射频MEMS并联开关射频性能的影响
2020 5th IEEE International Conference on Emerging Electronics (ICEE) Pub Date : 2020-11-26 DOI: 10.1109/icee50728.2020.9776699
Niharika Narang, P. Shrivastava, A. Basu, Pushparaj Singh
{"title":"Effect of Actuation electrode design on RF Performance of RF MEMS shunt switch","authors":"Niharika Narang, P. Shrivastava, A. Basu, Pushparaj Singh","doi":"10.1109/icee50728.2020.9776699","DOIUrl":"https://doi.org/10.1109/icee50728.2020.9776699","url":null,"abstract":"Reconfigurability in RF and microwave circuits can be achieved using RF switches. MEMS switches in RF provide high isolation, better return loss while consuming negligible power. These switches can control the flow of RF signals in the transmission line. The actuation electrode regulates the movement of a MEMS switch. Therefore, it becomes an important task to configure the actuation electrode to have a low impact on the RF signal. In this article, we have designed a unique configuration of actuation electrode biasing to achieve low loss and high RF performance. This designed configuration provides high performance and reduces the size of the structure due to change in the inductance and capacitance of the transmission line by the defect grounded structures (DGS). Insertion loss is 0.1419 dB, and the Return loss is 27.20 dB at 20GHz. Simulation is done in HFSS (Ansys). RF performance on the various substrate has also been observed to authenticate the design.","PeriodicalId":436884,"journal":{"name":"2020 5th IEEE International Conference on Emerging Electronics (ICEE)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129038513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Double Gate NCFET : A New Approach for Low Subthreshold Swing 双栅NCFET:低亚阈值摆幅的新方法
2020 5th IEEE International Conference on Emerging Electronics (ICEE) Pub Date : 2020-11-26 DOI: 10.1109/icee50728.2020.9776673
Mooli Shashank Reddy, Tejendra Dixit, K. P. Pradhan
{"title":"Double Gate NCFET : A New Approach for Low Subthreshold Swing","authors":"Mooli Shashank Reddy, Tejendra Dixit, K. P. Pradhan","doi":"10.1109/icee50728.2020.9776673","DOIUrl":"https://doi.org/10.1109/icee50728.2020.9776673","url":null,"abstract":"NCFETs(Negative Capacitance Field Effect Transistors) are commonly known for their Low Power Consumption[4]. As the name itself suggests that it uses a Negative Capacitance For the Voltage Amplification. This Amplification is due to the polarisation in the ferroelectric material, which is used as Negative Capacitance[5]. Due to the Orderly Alignment of the Dipoles in Ferroelectric material when an voltage is applied there will be an enhanced electric field which inturn enhances the voltage. So that there is an voltage amplification. This paper explores an approach to design NCFETS with a lower subthreshold swing and aslo details about the voltage amplification. This model is verified with several other model for an thin body, double-gate FET architecture.","PeriodicalId":436884,"journal":{"name":"2020 5th IEEE International Conference on Emerging Electronics (ICEE)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116707093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Characterization of Fe2NiO4 nanoparticles doped PDLC for applications in display technology 纳米Fe2NiO4掺杂PDLC在显示技术中的应用
2020 5th IEEE International Conference on Emerging Electronics (ICEE) Pub Date : 2020-11-26 DOI: 10.1109/icee50728.2020.9776985
A. Singh, A. Kumari, A. Sinha
{"title":"Characterization of Fe2NiO4 nanoparticles doped PDLC for applications in display technology","authors":"A. Singh, A. Kumari, A. Sinha","doi":"10.1109/icee50728.2020.9776985","DOIUrl":"https://doi.org/10.1109/icee50728.2020.9776985","url":null,"abstract":"Polymer Dispersed Liquid Crystal (PDLC) acts as a building block of optical material for light shutters. In this study, epoxy resins and nematic liquid crystal (5CB) were used to prepare the PDLC electro-optic shutter. The effect of doping with magnetic nanoparticles (NPs) of iron-nickel oxide (Fe2NiO4) in 0.33 wt.% concentration was investigated. The prepared samples were well characterized using polarizing optical microscopy, electro-optic, optical, and dielectric setup. The obtained experimental results manifest an enhancement in the electro-optic properties of the PDLC, making the Fe2NiO4 doped PDLC, a suitable choice for the display technology.","PeriodicalId":436884,"journal":{"name":"2020 5th IEEE International Conference on Emerging Electronics (ICEE)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115670521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fabrication of Binder-free TiO2 Nanoparticle Electrodes for Supercapacitor in Low-Power Electronic Applications 低功耗电子超级电容器用无粘结剂TiO2纳米颗粒电极的制备
2020 5th IEEE International Conference on Emerging Electronics (ICEE) Pub Date : 2020-11-26 DOI: 10.1109/icee50728.2020.9776669
Shalu Rani, Nagesh Kumar, Abhinav Tandon, Yogesh Sharma
{"title":"Fabrication of Binder-free TiO2 Nanoparticle Electrodes for Supercapacitor in Low-Power Electronic Applications","authors":"Shalu Rani, Nagesh Kumar, Abhinav Tandon, Yogesh Sharma","doi":"10.1109/icee50728.2020.9776669","DOIUrl":"https://doi.org/10.1109/icee50728.2020.9776669","url":null,"abstract":"In the present work, supercapacitor performance of binder-free TiO2 nanoparticles electrodes, fabricated via a facile, cost effective electrophoretic deposition (EPD) technique has been analyzed. To enhance the electrical conductivity and adhesion of coated TiO2 nanoparticles thin film over the graphite substrate, an optimized amount (2 wt. %) of multiwalled carbon nanotubes (MWCNTs) is added into the dispersion of TiO2 nanoparticles. Uniform and smooth surface morphology of fabricated electrodes has been analyzed using field emission scanning electron microscope (FESEM). The electrochemical analysis of the electrodes is done in a three-electrode configuration cell with 2M KOH electrolyte through cyclic voltammetry (CV), galvanostatic charge-discharge (GCD) and electrochemical impedance spectroscopy (EIS). Electrochemical analysis reveals that the best optimized TiO2 nanoparticles electrode having 2 wt.% MWCNTs displays an enhanced specific capacitance of $320 pm 5$ Fg−1 at 1 Ag−1 current density. The fabricated electrode displays a higher diffusion coefficient $sim 1.45times 10^{-10}text{cm}^{2}mathrm{s}^{-1}$ and a small relaxation time constant $(tau_{mathrm{o}}=89 text{ms})$ in 2M KOH. Moreover, fabricated TiO2 nanoparticles electrode maintains 87 % capacity retention after 1000 charge/discharge cycles. We believe this study would be helpful in the designing of practical supercapacitor devices for low-power electronic applications.","PeriodicalId":436884,"journal":{"name":"2020 5th IEEE International Conference on Emerging Electronics (ICEE)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124817373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SCAPS Modelling of solar cells: Deploying a back surface field SnS layer for performance upgradation 太阳能电池的SCAPS建模:为性能升级部署后表面场SnS层
2020 5th IEEE International Conference on Emerging Electronics (ICEE) Pub Date : 2020-11-26 DOI: 10.1109/icee50728.2020.9777010
P. Kumari, B. S. Sengar, Amitesh Kumar
{"title":"SCAPS Modelling of solar cells: Deploying a back surface field SnS layer for performance upgradation","authors":"P. Kumari, B. S. Sengar, Amitesh Kumar","doi":"10.1109/icee50728.2020.9777010","DOIUrl":"https://doi.org/10.1109/icee50728.2020.9777010","url":null,"abstract":"Cu2ZnSnS4 (CZTS) based thin-film photovoltaic (PV) cells are suitable candidates for PV cells since CZTS (as absorber material) has an easily tunable bandgap, is nontoxic and economical. Using the Back Surface Field (BSF) layer is one of the primary methods of upgrading the efficiency of PV cells. The BSF layer reduces the wastage of photo-generated electrons at the back recombination sink, and hence improves the efficiency of the cell. Engineering Mo/CZTS interface is very crucial for the performance of PV devices","PeriodicalId":436884,"journal":{"name":"2020 5th IEEE International Conference on Emerging Electronics (ICEE)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122693933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Heavy-Ion Induced Single Event Transients in Sub-7nm Bulk and SOI NSFETs 亚7nm块体和SOI nsfet中重离子诱导的单事件瞬态
2020 5th IEEE International Conference on Emerging Electronics (ICEE) Pub Date : 2020-11-26 DOI: 10.1109/icee50728.2020.9776740
C. Jha, Aarti Rathi, Pritam Yogi, K. Aditya, A. Dixit
{"title":"Heavy-Ion Induced Single Event Transients in Sub-7nm Bulk and SOI NSFETs","authors":"C. Jha, Aarti Rathi, Pritam Yogi, K. Aditya, A. Dixit","doi":"10.1109/icee50728.2020.9776740","DOIUrl":"https://doi.org/10.1109/icee50728.2020.9776740","url":null,"abstract":"In this paper, we investigate and report single event transient (SET) effects caused by heavy-ion on bulk and SOI nanosheet FETs (NSFETs) using Sentaurus TCAD heavy-ion model. The SET current in bulk and SOI NSFETs for different fin widths have also been compared and reported. Simulation results exhibit that SET peak current is higher in bulk NSFET compared to SOI NSFET, owing to its larger volume for charge collection in bulk devices. We have also considered different locations for a heavy-ion strike to study the worst-case scenario of SET current in NSFETs. It can be concluded that SET current increases when the location of heavy-ion strike shifts from the source contact to drain contact. In addition to this, the effect of the different angles of ion incidence on SET performance has been also analyzed. Finally, SET performance in bulk and SOI NSFETs has also been compared for different heavy-ion track radius.","PeriodicalId":436884,"journal":{"name":"2020 5th IEEE International Conference on Emerging Electronics (ICEE)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131814068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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