2021 IEEE 30th Asian Test Symposium (ATS)最新文献_第2页

On Modeling CMOS Library Cells for Cell Internal Fault Test Pattern Generation 基于CMOS库单元建模的单元内部故障测试图生成

2021 IEEE 30th Asian Test Symposium (ATS) Pub Date : 2021-11-01 DOI: 10.1109/ATS52891.2021.00030

X. Lin, Wu-Tung Cheng, Takeo Kobayashi, Andreas Glowatz

{"title":"On Modeling CMOS Library Cells for Cell Internal Fault Test Pattern Generation","authors":"X. Lin, Wu-Tung Cheng, Takeo Kobayashi, Andreas Glowatz","doi":"10.1109/ATS52891.2021.00030","DOIUrl":"https://doi.org/10.1109/ATS52891.2021.00030","url":null,"abstract":"As the manufactural technologies are moving to deep sub-micron process, the defects inside the design library cells occur more often during manufacture. Cell-Aware Testing (CAT) had been proposed to improve the test quality on detecting the cell internal defects. In CAT, the analog simulator is used to simulate the cell input combinations exhaustively for every defect to identify all the cell input combinations that detect the defects in the cells. However, it becomes less practical to handle the complex cells with large number of inputs and to consider multiple capture cycles because of the computational complexity of the analog simulation when processing the extremely large number of the input combinations. In this paper, we propose to model the design library cells as the ATPG library cells at the transistor level such that the existing ATPG tools can be used to generate the exhaustive test sets for every cell internal defect more efficiently. The generated test patterns are further divided into the hard-detection set and the soft-detection set. Only the test patterns from the soft-detection set need to be simulated by the analog simulator to verify the capability and the confidence level on detecting the defect. Using the proposed method can dramatically speed up the time-consuming step in the CAT flow, that is, for every defect to identify all input combinations that detect the defect through the analog simulation.","PeriodicalId":432330,"journal":{"name":"2021 IEEE 30th Asian Test Symposium (ATS)","volume":"257 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133210290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Investigation of 0.18μm CMOS Sensitivity to BTI and HCI Mechanisms under Extreme Thermal Stress Conditions 极端热应力条件下0.18μm CMOS对BTI和HCI机制的灵敏度研究

2021 IEEE 30th Asian Test Symposium (ATS) Pub Date : 2021-11-01 DOI: 10.1109/ATS52891.2021.00029

Yen Tran, T. Nomura, Mohamed Salim Cherchali, C. Tassin, Y. Deval, C. Maneux

引用次数: 1

[Copyright notice] (版权)

2021 IEEE 30th Asian Test Symposium (ATS) Pub Date : 2021-11-01 DOI: 10.1109/ats52891.2021.00003

引用次数: 0

CausalTester: Measuring the Consistency of Replicated Services via Causality Semantics CausalTester:通过因果语义度量复制服务的一致性

2021 IEEE 30th Asian Test Symposium (ATS) Pub Date : 2021-11-01 DOI: 10.1109/ATS52891.2021.00021

Yu Tang, Le Zhao, W. Yuan, Xu Wang

引用次数: 0

Polynomial Formal Verification of Prefix Adders 前缀加法器的多项式形式验证

2021 IEEE 30th Asian Test Symposium (ATS) Pub Date : 2021-11-01 DOI: 10.1109/ATS52891.2021.00027

Alireza Mahzoon, R. Drechsler

引用次数: 23

SeGa: A Trojan Detection Method Combined With Gate Semantics SeGa:一种结合门语义的木马检测方法

2021 IEEE 30th Asian Test Symposium (ATS) Pub Date : 2021-11-01 DOI: 10.1109/ATS52891.2021.00020

Yunying Ye, Shan Li, Haihua Shen, Huawei Li, Xiaowei Li

引用次数: 1

Further Analysis of Laser-induced IR-drop 激光诱导红外下降的进一步分析

2021 IEEE 30th Asian Test Symposium (ATS) Pub Date : 2021-11-01 DOI: 10.1109/ATS52891.2021.00028

W. Cruz, R. Viera, J. Dutertre, J. Rigaud, G. Hubert

{"title":"Further Analysis of Laser-induced IR-drop","authors":"W. Cruz, R. Viera, J. Dutertre, J. Rigaud, G. Hubert","doi":"10.1109/ATS52891.2021.00028","DOIUrl":"https://doi.org/10.1109/ATS52891.2021.00028","url":null,"abstract":"Studies on laser induced IR-drop are recent and still not much covered. Since laser-induced IR-drop can amplify the well-known effects of induced photoelectric currents in ICs, this work aims to present important characteristics of such effect. Understanding the characteristics and effects of laser induced IR-drop in ICs allows the elaboration of more accurate simulation models, and consequently helps in the design of countermeasures that mitigate the effects of laser illumination. Simulations and experiments were performed in order to understand the relationship of the laser pulse width and the decoupling capacitance of the power supply network with the induced IR-drop. The results showed that the maximum variation of the supply voltage depends on the laser pulse duration, and on other circuit characteristics, such as RLC parameters of the supply network. It was possible to observe by simulations and experiments that, for the proposed circuit, the maximum variation of the supply voltage occurred for a laser pulse greater than or equal to 1 μs. Regarding the decoupling capacitance variation, the results showed that for a decoupling capacitor up to 100 pF, the IR-drop becomes even more relevant with a variation up to 97% of VDD.","PeriodicalId":432330,"journal":{"name":"2021 IEEE 30th Asian Test Symposium (ATS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115183652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Lightweight Hardware-Based Memory Protection Mechanism on IoT Processors 基于轻量级硬件的物联网处理器内存保护机制

2021 IEEE 30th Asian Test Symposium (ATS) Pub Date : 2021-11-01 DOI: 10.1109/ATS52891.2021.00015

Hung-Yao Chi, Kuen-Jong Lee, Tzu-Chun Jao

{"title":"Lightweight Hardware-Based Memory Protection Mechanism on IoT Processors","authors":"Hung-Yao Chi, Kuen-Jong Lee, Tzu-Chun Jao","doi":"10.1109/ATS52891.2021.00015","DOIUrl":"https://doi.org/10.1109/ATS52891.2021.00015","url":null,"abstract":"As the Internet of Things (IoT) systems become more and more popular, many devices around life are now connected to the internet. While allowing large amounts of information to be transmitted and exchanged, sensitive information in IoTs also becomes vulnerable to leakage. Therefore the security of each device and network in IoT systems has become a critical issue. Many IoT devices are simple devices used for daily supplies; they cannot cost too much and must be lightweight. These devices are often controlled by simple Operating Systems (OS), some even in bare-metal environments without OS. In this paper we propose a lightweight memory security mechanism implemented mainly by hardware. This mechanism puts critical data in secure regions, and the processor can access the secure regions only after passing a hardware-based authentication process. Our method allows the processor to maintain high security without relying on the OS; hence even if the IoT device only has a bare-metal environment, it still can protect important data at a low cost. Experimental results show that a very high level of security can be achieved with only a very small extra delay and area overhead required.","PeriodicalId":432330,"journal":{"name":"2021 IEEE 30th Asian Test Symposium (ATS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114774754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Robust Fault-Tolerant Design Based on Checksum and On-Line Testing for Memristor Neural Network 基于校验和在线测试的记忆电阻神经网络鲁棒容错设计

2021 IEEE 30th Asian Test Symposium (ATS) Pub Date : 2021-11-01 DOI: 10.1109/ATS52891.2021.00017

Michihiro Shintani, Mamoru Ishizaka, M. Inoue

{"title":"Robust Fault-Tolerant Design Based on Checksum and On-Line Testing for Memristor Neural Network","authors":"Michihiro Shintani, Mamoru Ishizaka, M. Inoue","doi":"10.1109/ATS52891.2021.00017","DOIUrl":"https://doi.org/10.1109/ATS52891.2021.00017","url":null,"abstract":"The matrix-vector product is the most essential operation in the weight calculation of deep learning, and greatly impacts the calculation speed and power consumption of neural network circuits. A memristor is one of the most promising components used to efficiently develop matrix-vector products. However, it has been pointed out that memristors have a severely low write endurance limitation and large variation during operation owing to their manufacturing immaturity. While an algorithm-based fault tolerance method has thus far been proposed to enhance the reliability by applying checksum function and online testing, the effectiveness of such the function remains limited because it can apply only the forward propagation and multiple hard faults cannot be repaired. This paper proposes an extension of the conventional method to achieve a more robust fault-tolerant method for memristor-based neural network circuits. Numerical experiments using the Hopfield network and three-layered neural network demonstrate that the proposed method achieves 5.25% and 1.88% higher classification accuracies compared with a conventional fault-tolerant method, respectively.","PeriodicalId":432330,"journal":{"name":"2021 IEEE 30th Asian Test Symposium (ATS)","volume":"203 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124561966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Temperature-Aware Evaluation and Mitigation of Logic Soft Errors Under Circuit Variations 电路变化下的温度感知逻辑软误差评估与缓解

2021 IEEE 30th Asian Test Symposium (ATS) Pub Date : 2021-11-01 DOI: 10.1109/ATS52891.2021.00018

Warin Sootkaneung, S. Chookaew, S. Howimanporn

引用次数: 0