2021 IEEE 30th Asian Test Symposium (ATS)最新文献

{"title":"A Design of Approximate Voting Schemes for Fail-Operational Systems","authors":"H. Ichihara, Kazunori Yukihiro, Tomoo Inoue","doi":"10.1109/ATS52891.2021.00033","DOIUrl":"https://doi.org/10.1109/ATS52891.2021.00033","url":null,"abstract":"In safety critical systems, e.g., automotive systems, the concept of fail-operational is very important. In this paper we focus on an approximate voting scheme called IDMR (Inexact Double Modular Redundancy), which can detect an error of the output of the duplicated system and correct the error approximately if the significance of the error is within a certain limit; The systems with IDMR can operate continuously even if a fault occurs in the system, i.e., the systems are fail-operational. To enhance the ability of IDMR scheme, we propose an extended architecture for IDMR scheme, which is called E-IDMR (Extended IDMR). The proposed E-IDMR can correct large errors that cannot be corrected by IDMR, so that the systems with E-IDMR achieve higher fail-operational ability than those with IDMR. Application to automotive ABS and LKAS shows that the proposed E-IDMR is more effective for implementation of these fail-operational systems.","PeriodicalId":432330,"journal":{"name":"2021 IEEE 30th Asian Test Symposium (ATS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123234545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Application of Residue Sampling to RF/AMS Device Testing","authors":"Shogo Katayama, Yudai Abe, A. Kuwana, Koji Asami, M. Ishida, Ryuya Ohta, Haruo Kobayashi","doi":"10.1109/ATS52891.2021.00016","DOIUrl":"https://doi.org/10.1109/ATS52891.2021.00016","url":null,"abstract":"This paper describes the application of our previously proposed residue sampling circuit to RF/Analog Mixed-Signal (AMS) device testing. The residue sampling circuit provides high-frequency signal estimation using multiple low-frequency sampling circuits following an analog Hilbert filter and ADCs; the sampling frequencies are relatively prime. It is based on aliasing phenomena in the frequency domain for waveform sampling and the residue number theory. A high frequency cosine wave is provided as an input signal. Cosine and sine signals with the same frequency are generated by an analog Hilbert filter and are fed into sampling circuits with different (relatively prime) low sampling frequencies. Their analog outputs are analog-to-digital converted and complex FFT is performed on both. Since the high frequency signal is sampled with low frequency clocks, aliasing (spectrum folding) occurs. However, each aliased frequency is different because each sampling clock frequency is different in the sampling circuits. Based on the Chinese remainder theorem, this difference allows the input frequency to be estimated. High frequency resolution can be achieved over long time periods and large numbers of FFT points. We consider here applications to RF/AMS device testing; (i) two tone testing for high frequency narrow band devices, (ii) wireless communication device testing such as LTE, Bluetooth and (iii) wideband analog filter frequency characteristics testing. These considerations are supported by simulations.","PeriodicalId":432330,"journal":{"name":"2021 IEEE 30th Asian Test Symposium (ATS)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121408587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effective SAT-based Solutions for Generating Functional Sequences Maximizing the Sustained Switching Activity in a Pipelined Processor","authors":"N. I. Deligiannis, R. Cantoro, Tobias Faller, Tobias Paxian, B. Becker, M. Reorda","doi":"10.1109/ATS52891.2021.00025","DOIUrl":"https://doi.org/10.1109/ATS52891.2021.00025","url":null,"abstract":"During device testing, one of the aspects to be considered is the minimization of the switching activity of the circuit under test in order to steer clear of introducing problems due to device overheating. Nevertheless, there are also certain scenarios during which the maximization of switching activity of the circuit under test (CUT) or of certain parts of it could be proven beneficial e.g., during Burn-In (BI), where internal stress is often produced by applying suitable stimuli. This can be done in a functional manner based on Software-based Self-Test in order to avoid possible damages to the CUT and/or any kind of yield loss. However, the generation of suitable test programs for this task represents a non-trivial task. In this paper we consider a scenario where the circuitry to be stressed is a pipelined processor. We present a methodology, based on formal techniques, able to automatically generate the best functional stress stimuli, i.e., a short and repeatable sequence of assembly instructions, which is guaranteed to induce the maximum switching activity within a given target processor module over a pre-defined time period. For the purposes of our experiments we used the OpenRISC 1200. The gathered experimental results demonstrate the effectiveness of the developed method. In particular, we show that the time for generating the best instruction sequence is limited in most cases, while the generated sequence can always achieve a significantly higher sustained toggling activity than any other solution.","PeriodicalId":432330,"journal":{"name":"2021 IEEE 30th Asian Test Symposium (ATS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115972092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Twine Stack: A Hybrid Mechanism Achieving Less Cost for Return Address Protection","authors":"Qizhen Xu, Liwei Chen, Gang Shi","doi":"10.1109/ATS52891.2021.00014","DOIUrl":"https://doi.org/10.1109/ATS52891.2021.00014","url":null,"abstract":"Return-oriented programming(ROP) is a prevalent technique that targets return addresses to hijack control flow. To prevent such attack, researchers mainly focus on either Shadow Stack or MAC-based mechanisms(message code authentication). But Shadow Stack suffers from additional memory overhead and information leakage, while MAC-based mechanisms(e.g. Zipper Stack) impose high runtime overhead for MAC calculations.In this paper, we propose Twine Stack, a hybrid and efficient return address protection mechanism with lightweight hardware extension. It utilizes a tiny hardware shadow stack to realize a new multi-chain Zipper Stack. Specifically, each entry in the shadow stack stores a return address and its MAC in each chain, allowing queueing calculation with just one hash module. At meantime, some return address verifications could be done by comparison with the hardware shadow stack, instead of calculation again. We implemented Twine Stack on RISC-V architecture, and evaluated it on FPGA board. Our experiments show that Twine Stack reduces over 95% hash verifications, and imposes merely 1.38% performance overhead with an area overhead of 974 LUTs and 726 flip flops. The result demonstrates that our hybrid scheme mitigates the drawbacks of each separate scheme.","PeriodicalId":432330,"journal":{"name":"2021 IEEE 30th Asian Test Symposium (ATS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121600334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fault Analysis of the Beam Acceleration Control System at the European XFEL using Data Mining","authors":"Arne Grünhagen, J. Branlard, Annika Eichler, Gianluca Martino, Görschwin Fey, M. Tropmann-Frick","doi":"10.1109/ATS52891.2021.00023","DOIUrl":"https://doi.org/10.1109/ATS52891.2021.00023","url":null,"abstract":"The European X-Ray Free-Electron Laser (EuXFEL) relies like other high integrity systems on several sub systems. The Low Level Radio Frequency (LLRF) sub system of the EuXFEL is responsible for the correct acceleration of electron bunches. The LLRF system comprises several embedded components that are directly connected to the accelerator hardware. Due to the high complexity of the LLRF system, unforeseen machine trips occur regularly.In this work we built the basis for a mechanism that automatically identifies faulty behavior of the embedded components. To achieve that, we performed two different experiments, where a faulty behavior was artificially injected to the system. We analyzed the experiment data, performed a feature extraction and applied different machine learning methods. We used basic anomaly detection and basic clustering methods for identifying the faulty data elements. Additionally, we used a support vector machine for modelling the systems behavior. The selected algorithms are compared with respect to their ability to classify LLRF data correctly.","PeriodicalId":432330,"journal":{"name":"2021 IEEE 30th Asian Test Symposium (ATS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122448001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"GPU-Accelerated Timing Simulation of Systolic-Array-Based AI Accelerators","authors":"S. Holst, Lim Bumun, X. Wen","doi":"10.1109/ATS52891.2021.00034","DOIUrl":"https://doi.org/10.1109/ATS52891.2021.00034","url":null,"abstract":"Systolic arrays are currently used in autonomous systems such as self-driving cars to accelerate the enormous amount of matrix operations necessary for DNN inference. The reliability of such accelerators are of utmost importance since any loss in DNN accuracy due to erroneous calculations can have dire consequences. We propose a novel method to measure accuracy losses caused by arbitrary timing faults in systolic arrays. Our GPU-based simulation system enables for the first time a complete and accurate timing simulation of all inference-related matrix operations on large systolic arrays. A single consumer-grade GPU can simulate a LeNet-5 at a throughput of about 13s per inference. Furthermore, our simulation approach readily scales to larger DNNs and multiple GPUs.","PeriodicalId":432330,"journal":{"name":"2021 IEEE 30th Asian Test Symposium (ATS)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122630788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Towards a Secure Integrated Heterogeneous Platform via Cooperative CPU/GPU Encryption","authors":"Zhendong Wang, Rujia Wang, Zihang Jiang, Xulong Tang, S. Yin, Yang Hu","doi":"10.1109/ATS52891.2021.00032","DOIUrl":"https://doi.org/10.1109/ATS52891.2021.00032","url":null,"abstract":"Nowadays, emerging integrated heterogeneous platforms play major roles to host autonomous systems. However, the security issue that comes with such heterogeneous architectures has not been thoroughly explored and imposes great threats and vulnerabilities to these systems. We set out to explore the security issues for the heterogeneous architectures and the corresponding mitigation mechanisms. We investigate the side-channel timing attack in a modern integrated CPU/GPU platform and propose a CPU/GPU co-encryption mechanism CoENC to mitigate the timing attack to provide a secure platform for autonomous systems. Evaluations demonstrate CoENC can effectively enhance the security 29~44 times compared to the baseline with an extra 14%~31% latency overhead.","PeriodicalId":432330,"journal":{"name":"2021 IEEE 30th Asian Test Symposium (ATS)","volume":"519 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123132609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High Precision Measurement of Sub-Nano Ampere Current in ATE Environment","authors":"Keno Sato, Takayuki Nakatani, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Shogo Katayama, Gaku Ogihara, Daisuke Iimori, Yujie Zhao, Jianglin Wei, A. Kuwana, K. Hatayama, Haruo Kobayashi","doi":"10.1109/ATS52891.2021.00036","DOIUrl":"https://doi.org/10.1109/ATS52891.2021.00036","url":null,"abstract":"Background: In IoT system devices, currents become smaller and they have to operate for ten years with a coin cell battery. Then their accurate and fast measurement is required at the mass production shipping stage. However, the conventional method needs a large resistor (Rm, MΩ-order in Fig. 1) which makes the testing slow, and the ATE environment is noisy.Research Target: Our target is the development of a testing technique to measure the current in the order of nano or sub-nano ampere with high linearity in the noisy ATE environment and in short time as well as with only additional low cost built-out self-test (BOST) circuits.Approach: Fig. 2 shows the proposed current measurement circuits. The current under test is converted to the voltage through an op-amp and a resistor Rm of 10kΩ, and it is then converted to the AC voltage; these conversions are done with small BOST circuits. The AC voltage is amplified and converted to the digital signal through an AC amp, a sample/hold circuit and an ADC. FFT is performed and its power spectrum is calculated; the input current value is obtained. The resistor (Rm) of 10k generates spike noises which are spurious components in the power spectrum. However, usage of the sample/hold circuit reduces their effects. Thanks to the DC-AC conversion, the measurement accuracy is not degraded by the system noise in the low frequency region. The nano-ampere current and the resistor of 10kΩ produces several tens μV level voltage and our previous research in [1, 2] shows that the DC-AC conversion method can measure this level of the voltage accurately and in short time. Also, its multi-channel measurement is possible.Experiment Verification: Preliminary experiment with the prototype system in Fig. 2 was performed and its measured result is shown in Fig. 3. The measurement circuit gain in Fig. 2 was calibrated with 1.0nA input current (Iin), which corresponds to Vin of 10.0μV. Also an offset of 0.2μV due to electromotive force (EMF) was calibrated. We see in Fig. 3 that the proposed method can measure the current as low as 50pA. So far EMF limits the lowest measurable current. Fig. 4 shows 100 times of measurements for 1.0nA without averaging. Each measured current value is obtained by 1K-point FFT with 25.6 ksps, 16-bit ADC (myDAQ) usage and the measurement time of 40ms. The measured data is within 0.94nA to 1.07nA; the variation range is 0.13nAp−p.Conclusion: A method of fast and accurate current measurement as low as 50pA using IV conversion and DC-AC conversion in ATE environment has been developed.","PeriodicalId":432330,"journal":{"name":"2021 IEEE 30th Asian Test Symposium (ATS)","volume":"76 5-6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129715611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Detection of Stuck-at and Bridging Fault in Reversible Circuits using an Augmented Circuit","authors":"Mousum Handique, J. K. Deka, S. Biswas","doi":"10.1109/ATS52891.2021.00022","DOIUrl":"https://doi.org/10.1109/ATS52891.2021.00022","url":null,"abstract":"Low-power design is a major concern in the circuit design domain. The reversible circuit is an alternative for moving beyond the conventional ways of computing. For performing the high reliability and the correctness of the circuit, testing is necessary for evaluating the faults. This paper presents the fault detection method for classical fault models like stuck-at faults and bridging faults in reversible circuits using the negative-controlled augmented k-CNOT based circuit. We initially construct the n number of test vectors with n input lines for a given circuit. The constructed test vector sequences successfully attempt as the complete test set on the testable design augmented k-CNOT circuit for detecting faults. The proposed method applies to several benchmark circuits for detecting the stuck-at and bridging faults and also comparative analysis is prepared with some existing works.","PeriodicalId":432330,"journal":{"name":"2021 IEEE 30th Asian Test Symposium (ATS)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133893251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Positive and Negative Extra Clocking of LFSR Seeds for Reduced Numbers of Stored Tests","authors":"I. Pomeranz","doi":"10.1109/ATS52891.2021.00031","DOIUrl":"https://doi.org/10.1109/ATS52891.2021.00031","url":null,"abstract":"When test data compression uses a linear-feedback shift-register (LFSR) for on-chip decompression, stored tests consist of seeds for the LFSR. Extra clocking of an LFSR seed, bringing the LFSR to one of its next-states, was shown to allow several different tests to be applied based on every stored test, thus reducing the number of seeds that need to be stored, or increasing the fault coverage. Extra clocking that brings the LFSR to its next-states is referred to as positive extra clocking. Only this type of clocking was used earlier. This article suggests to replace a seed by a previous state of the LFSR as a way to increase the effectiveness of this approach without changing the test application process. The computation of previous states is referred to as negative extra clocking. The procedure described in this article uses negative extra clocking to replace seeds with previous states while adjusting the positive extra clocking of the seeds. Experimental results are presented for benchmark circuits to demonstrate the importance of negative extra clocking in reducing the number of seeds that need to be stored.","PeriodicalId":432330,"journal":{"name":"2021 IEEE 30th Asian Test Symposium (ATS)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114673892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}