2021 IEEE 30th Asian Test Symposium (ATS)最新文献_第3页

ChaoPIM: A PIM-based Protection Framework for DNN Accelerators Using Chaotic Encryption ChaoPIM:基于pim的DNN加速器混沌加密保护框架

2021 IEEE 30th Asian Test Symposium (ATS) Pub Date : 2021-11-01 DOI: 10.1109/ATS52891.2021.00013

Ning Lin, Xiaoming Chen, Chunwei Xia, Jing Ye, Xiaowei Li

引用次数: 1

Note on CapsNet-Based Wafer Map Defect Pattern Classification 关于基于capsnet的晶圆图缺陷模式分类的说明

2021 IEEE 30th Asian Test Symposium (ATS) Pub Date : 2021-11-01 DOI: 10.1109/ATS52891.2021.00019

Itsuki Fujita, Yoshikazu Nagamura, M. Arai, S. Fukumoto

引用次数: 2

Analyzing Transient Faults and Functional Error Rates of a RISC-V Core: A Case Study RISC-V内核瞬态故障与功能错误率分析

2021 IEEE 30th Asian Test Symposium (ATS) Pub Date : 2021-11-01 DOI: 10.1109/ATS52891.2021.00035

Dun-An Yang, J. Liou, Harry H. Chen

引用次数: 1

A Power Reduction Method for Scan Testing in Ultra-Low Power Designs 超低功耗设计中扫描测试的降低功耗方法

2021 IEEE 30th Asian Test Symposium (ATS) Pub Date : 2021-11-01 DOI: 10.1109/ATS52891.2021.00037

Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima

引用次数: 1

A Novel Compaction Approach for SBST Test Programs 一种新的SBST测试程序压缩方法

2021 IEEE 30th Asian Test Symposium (ATS) Pub Date : 2021-09-02 DOI: 10.1109/ATS52891.2021.00024

Juan-David Guerrero-Balaguera, J. E. R. Condia, M. Reorda

{"title":"A Novel Compaction Approach for SBST Test Programs","authors":"Juan-David Guerrero-Balaguera, J. E. R. Condia, M. Reorda","doi":"10.1109/ATS52891.2021.00024","DOIUrl":"https://doi.org/10.1109/ATS52891.2021.00024","url":null,"abstract":"In-field test of processor-based devices is a must when considering safety-critical systems (e.g., in robotics, aerospace, and automotive applications). During in-field testing, different solutions can be adopted, depending on the specific constraints of each scenario. In the last years, Self-Test Libraries (STLs) developed by IP or semiconductor companies became widely adopted. Given the strict constraints of in-field test, the size and time duration of a STL is a crucial parameter. This work introduces a novel approach to compress functional test programs belonging to an STL. The proposed approach is based on analyzing (via logic simulation) the interaction between the micro-architectural operation performed by each instruction and its capacity to propagate fault effects on any observable output, reducing the required fault simulations to only one. The proposed compaction strategy was validated by resorting to a RISC-V processor and several test programs stemming from diverse generation strategies. Results showed that the proposed compaction approach can reduce the length of test programs by up to 93.9% and their duration by up to 95%, with minimal effect on fault coverage.","PeriodicalId":432330,"journal":{"name":"2021 IEEE 30th Asian Test Symposium (ATS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125438959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Side-Channel Attacks on Triple Modular Redundancy Schemes 三模冗余方案的侧信道攻击

2021 IEEE 30th Asian Test Symposium (ATS) Pub Date : 2021-04-09 DOI: 10.1109/ATS52891.2021.00026

Felipe Almeida, L. Aksoy, J. Raik, S. Pagliarini

{"title":"Side-Channel Attacks on Triple Modular Redundancy Schemes","authors":"Felipe Almeida, L. Aksoy, J. Raik, S. Pagliarini","doi":"10.1109/ATS52891.2021.00026","DOIUrl":"https://doi.org/10.1109/ATS52891.2021.00026","url":null,"abstract":"Triple Modular Redundancy (TMR) is a well-known fault tolerance technique for avoiding errors in the Integrated Circuits (ICs) and it has been used in a wide range of applications. The TMR technique employs three instances of circuits realizing concurrently the same functionality whose outputs are compared through a majority voter. On the other hand, Side-Channel Attacks (SCAs) are powerful techniques to extract secret information from ICs based on the data collected from security critical operations. Over the years, the interplay between security and reliability is poorly studied. In this paper, we explore the performance of SCAs on the well-known Advanced Encryption Standard (AES) and its different realizations using the TMR technique. In this work, three implementations of the AES design under the TMR scheme are used and an SCA, which can collect power dissipation data from the physical netlist through simulations, is developed. The experimental results show that the TMR technique can increase the computation time of SCAs and more importantly, the use of functionally equivalent, but physically and structurally different instances in the TMR scheme can make it impossible for SCAs to discover the secret key.","PeriodicalId":432330,"journal":{"name":"2021 IEEE 30th Asian Test Symposium (ATS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125847508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Tutorials 教程

2021 IEEE 30th Asian Test Symposium (ATS) Pub Date : 2019-06-01 DOI: 10.1109/ISSCC.2017.7870478

A. Sheikholeslami

引用次数: 0