{"title":"电路变化下的温度感知逻辑软误差评估与缓解","authors":"Warin Sootkaneung, S. Chookaew, S. Howimanporn","doi":"10.1109/ATS52891.2021.00018","DOIUrl":null,"url":null,"abstract":"While supply voltage and frequency directly affect circuit soft errors, thermal response from tuning these two parameters also provides a moderate side effect. This study firstly improves the accuracy of logic soft error estimation by taking into consideration the thermal impact from supply voltage and frequency variations. In the presence of the inversion of the temperature effect where the drive current of some modern designs increases at high temperature, we also take a benefit of this effect to develop a novel soft error mitigation technique by adaptively regulating the chip temperature. This technique can moderately reduce high soft error rate of combinational blocks during low voltage operation with neglectable power overhead.","PeriodicalId":432330,"journal":{"name":"2021 IEEE 30th Asian Test Symposium (ATS)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Temperature-Aware Evaluation and Mitigation of Logic Soft Errors Under Circuit Variations\",\"authors\":\"Warin Sootkaneung, S. Chookaew, S. Howimanporn\",\"doi\":\"10.1109/ATS52891.2021.00018\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"While supply voltage and frequency directly affect circuit soft errors, thermal response from tuning these two parameters also provides a moderate side effect. This study firstly improves the accuracy of logic soft error estimation by taking into consideration the thermal impact from supply voltage and frequency variations. In the presence of the inversion of the temperature effect where the drive current of some modern designs increases at high temperature, we also take a benefit of this effect to develop a novel soft error mitigation technique by adaptively regulating the chip temperature. This technique can moderately reduce high soft error rate of combinational blocks during low voltage operation with neglectable power overhead.\",\"PeriodicalId\":432330,\"journal\":{\"name\":\"2021 IEEE 30th Asian Test Symposium (ATS)\",\"volume\":\"58 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE 30th Asian Test Symposium (ATS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS52891.2021.00018\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE 30th Asian Test Symposium (ATS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS52891.2021.00018","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Temperature-Aware Evaluation and Mitigation of Logic Soft Errors Under Circuit Variations
While supply voltage and frequency directly affect circuit soft errors, thermal response from tuning these two parameters also provides a moderate side effect. This study firstly improves the accuracy of logic soft error estimation by taking into consideration the thermal impact from supply voltage and frequency variations. In the presence of the inversion of the temperature effect where the drive current of some modern designs increases at high temperature, we also take a benefit of this effect to develop a novel soft error mitigation technique by adaptively regulating the chip temperature. This technique can moderately reduce high soft error rate of combinational blocks during low voltage operation with neglectable power overhead.