On Modeling CMOS Library Cells for Cell Internal Fault Test Pattern Generation

Abstract

As the manufactural technologies are moving to deep sub-micron process, the defects inside the design library cells occur more often during manufacture. Cell-Aware Testing (CAT) had been proposed to improve the test quality on detecting the cell internal defects. In CAT, the analog simulator is used to simulate the cell input combinations exhaustively for every defect to identify all the cell input combinations that detect the defects in the cells. However, it becomes less practical to handle the complex cells with large number of inputs and to consider multiple capture cycles because of the computational complexity of the analog simulation when processing the extremely large number of the input combinations. In this paper, we propose to model the design library cells as the ATPG library cells at the transistor level such that the existing ATPG tools can be used to generate the exhaustive test sets for every cell internal defect more efficiently. The generated test patterns are further divided into the hard-detection set and the soft-detection set. Only the test patterns from the soft-detection set need to be simulated by the analog simulator to verify the capability and the confidence level on detecting the defect. Using the proposed method can dramatically speed up the time-consuming step in the CAT flow, that is, for every defect to identify all input combinations that detect the defect through the analog simulation.