Yen Tran, T. Nomura, Mohamed Salim Cherchali, C. Tassin, Y. Deval, C. Maneux
{"title":"Investigation of 0.18μm CMOS Sensitivity to BTI and HCI Mechanisms under Extreme Thermal Stress Conditions","authors":"Yen Tran, T. Nomura, Mohamed Salim Cherchali, C. Tassin, Y. Deval, C. Maneux","doi":"10.1109/ATS52891.2021.00029","DOIUrl":null,"url":null,"abstract":"Bias temperature instability (BTI) and hot carrier injection (HCI) are both prominent reliability concerns for integrated circuits (ICs). In this paper, we investigated these failure mechanisms on 0.18μm CMOS (Complementary Metal-Oxide-Semiconductor) submitted to severe temperatures (150°C and 210°C) for long period of stress (up to 2,000 hours). Additionally, the transistors were applied dedicated stress conditions to activate the intrinsic HCI and BTI wear-out mechanisms. The aging laws were proposed based on these experimental results and implemented into the commercial software tool for further investigation at logic circuit level.","PeriodicalId":432330,"journal":{"name":"2021 IEEE 30th Asian Test Symposium (ATS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE 30th Asian Test Symposium (ATS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS52891.2021.00029","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Bias temperature instability (BTI) and hot carrier injection (HCI) are both prominent reliability concerns for integrated circuits (ICs). In this paper, we investigated these failure mechanisms on 0.18μm CMOS (Complementary Metal-Oxide-Semiconductor) submitted to severe temperatures (150°C and 210°C) for long period of stress (up to 2,000 hours). Additionally, the transistors were applied dedicated stress conditions to activate the intrinsic HCI and BTI wear-out mechanisms. The aging laws were proposed based on these experimental results and implemented into the commercial software tool for further investigation at logic circuit level.