2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)最新文献

{"title":"Forced-resonance test technique for multiple wirebonds in electronic packages","authors":"S. Kannan, Bruce C. Kim, F. Taenzler","doi":"10.1109/EPTC.2012.6507157","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507157","url":null,"abstract":"This paper presents a low-cost test technique for testing multiple wirebonds in electronic packages. Multiple wirebonds are commonly used to reduce the net inductance of wirebonds and achieve lower signal transmission losses. However, if one of the wirebonds is broken then it is extremely difficult to identify it. We have developed a low-cost test technique based on the forced-resonance principle for testing multiple wirebonds in electronic packages. A prototype test setup has been built using two test pads with four parallel wirebonds between the test pads. Our test technique was able to identify when one or more wirebonds were broken. This test technique is highly accurate and is a very low-cost alternative when compared to expensive X-ray imaging systems or bond-pull testers.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"453 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122946262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study on creep fatigue behaviour of soft solders die attach for power package applications","authors":"Dandong Ge, F. Che, Yik Siong Tay, S. L. Gan, M. Yazid","doi":"10.1109/EPTC.2012.6507055","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507055","url":null,"abstract":"Soft solder die attach is a widely used process for power and high-reliability automotive devices because soft solder has excellent heat-dissipation properties and outstanding robustness against delamination compared to traditional epoxy die attach. However, the creep-fatigue failure is one typical failure mechanism for solder material under thermal cycling. So it is essential to to understand the solder failure due to soft solder creep fatigue behavior. In this work, tensile creep tests for two soft solders, solder A and B, have been conducted at various temperatures and stress levels using a Dynamic Mechanical Analyzer (DMA). Creep constitutive models were developed and the material constants of the model were determined based on experimental results for both solders. The creep constitutive models were implemented in finite element analysis (FEA) to investigate the creep behavior of solder in the power packages for the evaluation of package reliability. Results show that solder A has better creep resistance than solder B, which indicates that the package with using solder A should have higher creep fatigue reliability than package with using solder B when subjected to thermal cycling. The storage modulus, liquidus temperature/solidus temperature for two types of solders were also measured by DMA and Differential Scanning Calorimetry (DSC), respectively.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"186 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132044299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of new TSV structure composing of intermetallic compounds","authors":"Daquan Yu, Xiaoyang Liu, R. He, X. Jing, Chongshen Song, Fengwei Dai, Yu Sun, L. Wan","doi":"10.1109/EPTC.2012.6507108","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507108","url":null,"abstract":"TSV was regarded as the core technology enabling 3D IC integration. For volume production, the requirement of low-cost TSV fabrication process was a big challenge. In order to find a fast filling method, new Cu plating solutions are desirable and some new filling method using solder, Cu cored solder ball were studied. A new TSV structure composed of intermetallic compounds (IMCs) was proposed in present paper and the manufacturing process was introduced. To form such a TSV structure, it needs to fill liquid solder into the vias and accelerate the inter-diffusion of solder and metal on the sidewall of the vias by annealing. The feasibility of the formation of IMC TSVs was studied using SnPb solder. The solder was filled into the vias in which partial annular Cu layer was plated. Successful voids free filling with thin protrusion of solder material on the top of the vias was achieved. Finite element analysis (FEA) of TSV filling with Cu, solder and Sn-based IMC were carried out and the results showed that the IMC filled TSVs can get comparable or even lower stress depending on the CTE of the IMCs. According to present results, it can be concluded that the IMC TSVs have the following merits: fast and low cost forming process, good high temperature stability and the lower stress.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134030634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Roll-to-roll (R2R) hot embossing for structuring 3D microstructures on polymer films","authors":"X. Shan, M. B. Mohahidin, A. Lu","doi":"10.1109/EPTC.2012.6507146","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507146","url":null,"abstract":"Large area polymer films with patterned microstructures are expected to be widely used in various areas, such as functional optical films for flexible displays, lighting devices as well as structured films for microfluidic components. Large area embossing is a promising method for patterning microstructures on polymer substrates. We have investigated the process feasibility of roll-to-roll hot embossing as well as roll-to-plate hot embossing for large area, high-volume fabrication of microstructures on polymer substrates. Micro pillar (with diameter of 50μm) arrays were formed on polypropylene films via both roll-to-roll and roll-to-plate hot embossing. In this paper, we will report our achievement in roll-to-roll process study and explore potential industrial applications.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"447 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134435034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability of UHF RFID tags in humid environments","authors":"K. Saarinen, L. Frisk","doi":"10.1109/EPTC.2012.6507074","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507074","url":null,"abstract":"Radio frequency identification (RFID) is an emerging technology in the field of identification and security. With RFID tags it is possible to identify objects individually and reliably using radio waves. However, due to numerous applications, RFID tags are exposed to various environmental conditions which may impair their reliability. Long-term reliability is generally studied using accelerated environmental tests. In earlier studies a combination of high humidity and high temperature has been found to be very harmful to RFID tags. Consequently, in this study failure times and mechanisms between three accelerated humidity tests were compared to find a test which is most suitable for RFID tags. A passive ultra high frequency (UHF) RFID tag with a polyethylene terephthalate (PET) substrate was tested using two constant humidity tests and a humidity cycling test. According to this study, the selection of test conditions for reliability studies in humid environments should be carefully considered. PET substrate is susceptible to hydrolysis when a combination of high humidity and high temperature is present. Consequently, a standard 85°C/85% test is very harsh for RFID tags with PET substrate. On the other hand if a cycling test is used instead of a constant test to acclerate the test, the failure mechanism may alter. Therefore it is important to investigate the effects of changing humidity, but a constant humidity test cannot be directly replaced by the faster humidity cycling test due to the different stresses caused by the tests.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"212 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132195559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Process development for thick polysilicon film deposition","authors":"Tang Kum Cheong, Aloysius Tan Kai Yeow, Cheam Daw Don","doi":"10.1109/EPTC.2012.6507184","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507184","url":null,"abstract":"The deposition of thick (> 2 μm) polycrystalline silicon films on silicon wafer substrates can result in high incidences — more than half of wafers processed — of wafer breakage, the consequence of which is undesirable contamination of the deposition reactor arising from a spike in stray particles originating from the broken wafers. Even if the processed wafers remain intact, they may turn fragile and thus, unsuitable for further handling and processing. This paper describes the process development for the deposition of 3 μm polysilicon films, achieved with less than one-tenth of wafers broken, through epitaxial low pressure chemical vapor deposition. We found a two-step approach — deposit 2 μm followed by an overlying 1 μm polysilicon film — instrumental in reducing the occurrence of wafer breakage while ensuring the electrical homogeneity of the film.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131973274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Polymeric reinforcement approaches and materials selection to improve board-level drop reliability of SnAgCu soldered area array packages","authors":"Hongbin Shi, Cuihua Tian, M. Pecht, T. Ueda","doi":"10.1109/EPTC.2012.6507082","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507082","url":null,"abstract":"The board-level drop performance of area array package (AAP) assemblies is becoming increasingly critical due to the shift from desktop to mobile computing. Furthermore, challenges have arisen from the introduction of lead-free solders and miniaturization of solder joint dimensions. Polymeric reinforcement of AAPs offers a solution for drop reliability concerns. However, polymeric reinforcement increases the unit manufacturing cost of materials, capital equipment, cycle time, and rework. All of the polymeric reinforcement approaches, such as full capillary flow underfill (FCFU), partial capillary flow underfill (PCFU), edge bond adhesive (EBA), and corner bond adhesive (CBA), improve the drop reliability of lead-free fine-pitch AAP assemblies. However, the use of a polymeric reinforcement strategy with improper implementation and/or material properties may cause an unnecessary rise in manufacturing costs and/or cause the assemblies to fail to meet the drop performance requirements of a specific application. This study compares the different polymeric reinforcement approaches (FCFU, PCFU, EBA, and CBA) and material properties for AAPs using a vertical free drop test. One set of AAP assemblies with no polymeric reinforcement was tested as the control. The test results indicated that the drop performance of reinforced CSP assemblies increased with the use of better polymeric reinforcement material volume and modulus and higher adhesive strength of the materials. The components closer to outer edges of the PCB were more prone to failure compared to the components at the center of the PCB. In addition to the failure criteria based on daisy-chain resistance, the drop impact life based on the CSPs that fell of the PCBs can also be used simply to compare the performance of different polymeric reinforcement strategies. Failure analysis demonstrated that the dominant failure mode was brittle fracture at the CSP IMC/solder interface for all the test groups except the underfilled samples. However, the percentage of the PCB pad cratering failure mode significantly increased with the application of polymeric reinforcement materials.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132643507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fine pitch solder-less bonding using ultrasonic technique","authors":"S. Chong, J. Aw, Daniel Ismael Cereno, L. Siow, C. G. Koh, D. Witarsa, S. Vempati, T. Chai","doi":"10.1109/EPTC.2012.6507120","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507120","url":null,"abstract":"Industry is adapting micro-bumps in the device structures in order to having module with multiple functions and capabilities within smaller area. Micro-bumps is coated with Tin (Sn) cap to facilitates solder interconnects formation between the chip and substrate. Electrochemical migration failure is a known issue related to flux residue on the solder joints after the thermal compression of the chip with solder cap micro-bumps on substrate. Electromigration is another issue related to shrinking interconnects. It is related to atomic displacement in a conductor line due to an applied current. In this study, the micro bumps are directly bonded to the substrate without solder cap and thus there is no electro migration failure concern. The chip used in this study is of size 7mm × 7mm × 0.05mm and consists of peripheral micro-solder bumps at 40μm pitch with no solder cap. Ultra-sonic process was adopted to form the direct metal to metal joint between the chip and substrate. Ultrasonic process offered several advantages such as lower bonding temperature and shorter bonding duration over thermal compression process. However, the US process demand bumps with good co-planity of less than 0.6μm and good surface finishing. The copper bumps were coated either with TiAu, ENEPIG, and ENEP to prevent oxidation occurring during the bonding process. Detail DOE experiment was conducted to evaluate the bonding quality. Shear test and x-section analysis revealed that chips coated with either TiAu or ENEPIG could form a bond on silicon substrate coated with TiAu with optimized US parameters. The developed US bonding process successfully demonstrated on C2C application.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117298037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enabling thin packages with embeded components: A market arrives","authors":"E. J. Vardaman, L. Matthew, Karen E. Carpenter","doi":"10.1109/EPTC.2012.6507094","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507094","url":null,"abstract":"As companies realize that alternatives to 3D TSV die stacks are needed for commercial products, many companies are moving into production with embedded components in IC package substrates. The use of embedded die enables the production of a thin package that meets critical requirements of mobile products. Embedded components are found in many different configurations. Package-on-package is one of the latest package types to make use of embedded components. Some companies will embed active components in the substrate using a lamination process while others have adopted different manufacturing methods. Embedded actives are just one example of production packages, and there are applications that also use embedded formed resistors or capacitors, while others embed discrete passive components. This presentation examines the drivers for today's embedded component applications and how today's developments differ from technology introduced in the past.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122521663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and implementation of magnetically coupled current probe for monitoring simultaneous switching current in package","authors":"Changhyun Cho, Jonghyun Cho, Jonghoon J. Kim, Joungho Kim, J. Pak","doi":"10.1109/EPTC.2012.6507060","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507060","url":null,"abstract":"In this paper, we present a new embedded current probe that can support measurement-based approach for extracting switching current waveform that was injected into power distribution network (PDN). The proposed embedded current probing structure utilizes magnetic coupling behavior between primary conducting via and secondary toroidal coil structure surrounding and it can be used as a sensor which relates the induced voltage across toroidal coil to the switching current of conducting via. This paper will present characterization of magnetic coupling behavior of proposed embedded current probing structure, demonstration of proposed current extraction method by implementing the current probing structure in a board level PDN and validation of SSN analysis by applying the extracted current waveform through the simulation and measurement result.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128964482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}