2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)最新文献

{"title":"Fine pitch solder-less bonding using ultrasonic technique","authors":"S. Chong, J. Aw, Daniel Ismael Cereno, L. Siow, C. G. Koh, D. Witarsa, S. Vempati, T. Chai","doi":"10.1109/EPTC.2012.6507120","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507120","url":null,"abstract":"Industry is adapting micro-bumps in the device structures in order to having module with multiple functions and capabilities within smaller area. Micro-bumps is coated with Tin (Sn) cap to facilitates solder interconnects formation between the chip and substrate. Electrochemical migration failure is a known issue related to flux residue on the solder joints after the thermal compression of the chip with solder cap micro-bumps on substrate. Electromigration is another issue related to shrinking interconnects. It is related to atomic displacement in a conductor line due to an applied current. In this study, the micro bumps are directly bonded to the substrate without solder cap and thus there is no electro migration failure concern. The chip used in this study is of size 7mm × 7mm × 0.05mm and consists of peripheral micro-solder bumps at 40μm pitch with no solder cap. Ultra-sonic process was adopted to form the direct metal to metal joint between the chip and substrate. Ultrasonic process offered several advantages such as lower bonding temperature and shorter bonding duration over thermal compression process. However, the US process demand bumps with good co-planity of less than 0.6μm and good surface finishing. The copper bumps were coated either with TiAu, ENEPIG, and ENEP to prevent oxidation occurring during the bonding process. Detail DOE experiment was conducted to evaluate the bonding quality. Shear test and x-section analysis revealed that chips coated with either TiAu or ENEPIG could form a bond on silicon substrate coated with TiAu with optimized US parameters. The developed US bonding process successfully demonstrated on C2C application.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117298037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Forced-resonance test technique for multiple wirebonds in electronic packages","authors":"S. Kannan, Bruce C. Kim, F. Taenzler","doi":"10.1109/EPTC.2012.6507157","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507157","url":null,"abstract":"This paper presents a low-cost test technique for testing multiple wirebonds in electronic packages. Multiple wirebonds are commonly used to reduce the net inductance of wirebonds and achieve lower signal transmission losses. However, if one of the wirebonds is broken then it is extremely difficult to identify it. We have developed a low-cost test technique based on the forced-resonance principle for testing multiple wirebonds in electronic packages. A prototype test setup has been built using two test pads with four parallel wirebonds between the test pads. Our test technique was able to identify when one or more wirebonds were broken. This test technique is highly accurate and is a very low-cost alternative when compared to expensive X-ray imaging systems or bond-pull testers.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"453 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122946262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enabling thin packages with embeded components: A market arrives","authors":"E. J. Vardaman, L. Matthew, Karen E. Carpenter","doi":"10.1109/EPTC.2012.6507094","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507094","url":null,"abstract":"As companies realize that alternatives to 3D TSV die stacks are needed for commercial products, many companies are moving into production with embedded components in IC package substrates. The use of embedded die enables the production of a thin package that meets critical requirements of mobile products. Embedded components are found in many different configurations. Package-on-package is one of the latest package types to make use of embedded components. Some companies will embed active components in the substrate using a lamination process while others have adopted different manufacturing methods. Embedded actives are just one example of production packages, and there are applications that also use embedded formed resistors or capacitors, while others embed discrete passive components. This presentation examines the drivers for today's embedded component applications and how today's developments differ from technology introduced in the past.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122521663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Microstructure and plating thickness analysis of different surface finished plated printed circuit boards","authors":"Tama Fouzder, Y. Chan, Daniel K. Chan","doi":"10.1109/EPTC.2012.6507039","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507039","url":null,"abstract":"Different surface finished lead-free electroplated Cu substrates were prepared using an electrolytic process jointly developed for special applications. The surface morphology and plated layer thicknesses were investigated using atomic force microscope (AFM) and seanning electron microscope (SEM). From SEM micrographs, it was confirmed that the plated layers i.e., Au/Ni and Ag/Ni were well deposited on Cu substrates uniformly. In addition, the plated layer thicknesses were increased with an increasing processing temperature. The average Au/Ni p lated layers thicknesses atplated temperatures of30°C, 40°C and 5 0°C were about 0.67μm, 0.71μm and 0.77 μm, respectively. On the other hand, the average Ag/Ni plated layers thicknesses at plated temperatures of 10°C, 20°C and 30°C were about 6.5μm, 7.7μm and 8.4μm, respectively. From AFM observations, it was confirmed that the plated layer appeared to have a very smooth surface without any defects such as cra cks, delamination etc., confirming the successful application of the specially developed electrolytic process.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129216839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Wafer level packaging of RF MEMS devices using TSV interposer technology","authors":"V. N. Sekhar, J. Toh, Jin Cheng, J. Sharma, S. Fernando, Chen Bangtao","doi":"10.1109/EPTC.2012.6507083","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507083","url":null,"abstract":"This paper presents the design, fabrication and characterization of MEMS wafer level packaging (WLP) with TSV based silicon interposer as cap wafer. High resistivity Si wafers have been used for TSV interposer fabrication mainly to minimize the intrinsic loss of RF MEMS device due to packaging. During development of this RF MEMS WLP, many key challenging processes have been developed such as, high aspect ratio TSV fabrication, double side RDL fabrication, thin wafer handling of TSV interposer and optimization of Au-Sn based TLP bonding. There are several fabrication steps involved in the actual process flow as, a) TSV fabrication and front side RDL patterning and passivation, b) Wafer thinning and backside RDL patterning and passivation c) UBM/ seal ring solder deposition and cavity formation, and d) TLP based wafer bonding of cap TSV interposer wafer with MEMS CPW wafer. Different CPW designs with three passivation schemes have been fabricated mainly to study the effect of passivation on insertion loss and ultimately quantify the packaging insertion loss. In pre-bonding testing, effect of passivation on insertion loss is thoroughly studied. After successful fabrication of the WLP, loss of RF device characteristics due to packaging has been studied. Before and after packaging, S-parameter measurements performed on coplanar waveguides (CPW). Amongst different passivation schemes, CPW structures with poly-silicon passivation have shown better performance.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129534625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Processing of ultrathin wafers for power chip applications","authors":"Amarjit Dhadda, Robert M. Montgomery, P. Jones, Jason Heirene, Rachel Kuthakis, F. Bieck","doi":"10.1109/EPTC.2012.6507162","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507162","url":null,"abstract":"Providing thinner and thinner Silicon is one of the key challenges in today's semiconductor manufacturing. The thinner the wafer and thus the die, the thinner the package can be designed. Getting thinner devices is also a necessary precondition for Trough Silicon Via (TSV) technology, in which a thin wafer is needed in order to create through-contacts in the die. While for standard wafer applications the driver for thinner Silicon wafers may be considered as “geometrical”, this is not the case for power chip application. Here, the main driver for using thinner Silicon in powerchip applications is directly linked to device performance. As the Rds(on) is primarily a function of the device thickness and thus the wafer thickness, producing thinner Silicon provides not only geometrical advantages in the packaging process, but especially better performing devices. In order to fullill the demand for thinner and thus improved devices, International Rectifier (IR) has recently installed a 200 mm line for ultrathin wafers. In this paper, we will describe and discuss the thinning process that is implemented at IR.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127639617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability of isotropic electrically conductive adhesives under condensing humidity testing","authors":"L. Frisk, S. Lahokallio, M. Mostofizadeh, J. Kiilunen, K. Saarinen","doi":"10.1109/EPTC.2012.6507073","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507073","url":null,"abstract":"Electrically conductive adhesives (ECA) are considered to be one of the future technologies due to their potential for low cost, high reliability, and simple processing. Additionally, an important advantage with ECA materials is the possibility for low bonding temperature. Therefore, they are especially well suited for low cost applications. ECA materials are prepared by mixing polymer matrix with electrically conductive particles. In isotropic conductive adhesives (ICA) concentration of the conductive particles is high and they conduct in all directions. Several materials can be used to manufacture ICAs. The most widely used ICAs in the electronics industry are silver-filled epoxies, which also provide a high level of thermal conductivity. However, other polymers can also be used. All polymer materials used in ICAs absorb moisture, which affects their mechanical behavior. Additionally, the electrical properties of the ICA may change. Therefore it is important to study how different ICA materials behave under humid conditions. Especially, if the humidity levels are high, these changes may occur very rapidly. In this work 14 different commercial ICA materials were studied under condensing humidity conditions. To study the behavior of the ICAs they were used to attach zero ohm resistors onto FR-4 test boards. To study the effect of glob top on the behavior of the ICAs, two additional test series were assembled with two epoxy ICAs using a glop top material to protect the components and the interconnections. Marked changes were seen in the resistance values of the test samples during the test. Additionally, considerable variation was seen between the ICAs. Some ICAs showed increased resistance values very quickly after the testing was started. The two ICAs not shown did not show failures during testing.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128750557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Polymeric reinforcement approaches and materials selection to improve board-level drop reliability of SnAgCu soldered area array packages","authors":"Hongbin Shi, Cuihua Tian, M. Pecht, T. Ueda","doi":"10.1109/EPTC.2012.6507082","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507082","url":null,"abstract":"The board-level drop performance of area array package (AAP) assemblies is becoming increasingly critical due to the shift from desktop to mobile computing. Furthermore, challenges have arisen from the introduction of lead-free solders and miniaturization of solder joint dimensions. Polymeric reinforcement of AAPs offers a solution for drop reliability concerns. However, polymeric reinforcement increases the unit manufacturing cost of materials, capital equipment, cycle time, and rework. All of the polymeric reinforcement approaches, such as full capillary flow underfill (FCFU), partial capillary flow underfill (PCFU), edge bond adhesive (EBA), and corner bond adhesive (CBA), improve the drop reliability of lead-free fine-pitch AAP assemblies. However, the use of a polymeric reinforcement strategy with improper implementation and/or material properties may cause an unnecessary rise in manufacturing costs and/or cause the assemblies to fail to meet the drop performance requirements of a specific application. This study compares the different polymeric reinforcement approaches (FCFU, PCFU, EBA, and CBA) and material properties for AAPs using a vertical free drop test. One set of AAP assemblies with no polymeric reinforcement was tested as the control. The test results indicated that the drop performance of reinforced CSP assemblies increased with the use of better polymeric reinforcement material volume and modulus and higher adhesive strength of the materials. The components closer to outer edges of the PCB were more prone to failure compared to the components at the center of the PCB. In addition to the failure criteria based on daisy-chain resistance, the drop impact life based on the CSPs that fell of the PCBs can also be used simply to compare the performance of different polymeric reinforcement strategies. Failure analysis demonstrated that the dominant failure mode was brittle fracture at the CSP IMC/solder interface for all the test groups except the underfilled samples. However, the percentage of the PCB pad cratering failure mode significantly increased with the application of polymeric reinforcement materials.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132643507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Flow modeling of die attach process and the optimization of process parameters in advance packaging","authors":"L. Ji, L. Wai, Min Woo Daniel Rhee","doi":"10.1109/EPTC.2012.6507111","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507111","url":null,"abstract":"This paper presents a new numerical model to characterize the die attach process in the advance packaging. With its successful application on a 5 mm by 5 mm with 70um thickness die attached to the substrate, final fillet shape of the die attach material is predicted for various process conditions. Focuses have been given on the die attach material over flow on the die top surface. The contamination on the die top surface may cause failures in the subsequent processes. The simulation results were compared with the experiment. Good match was obtained. Moreover, process window for a given amount die attach material was established through the simulation and the corresponding bonding force that will not cause die attach material over flow was predicted. Key advantage of this numerical study is to give the insights into process parameters and provide initial process window to prevent die attach over flow.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128593376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Process development for thick polysilicon film deposition","authors":"Tang Kum Cheong, Aloysius Tan Kai Yeow, Cheam Daw Don","doi":"10.1109/EPTC.2012.6507184","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507184","url":null,"abstract":"The deposition of thick (> 2 μm) polycrystalline silicon films on silicon wafer substrates can result in high incidences — more than half of wafers processed — of wafer breakage, the consequence of which is undesirable contamination of the deposition reactor arising from a spike in stray particles originating from the broken wafers. Even if the processed wafers remain intact, they may turn fragile and thus, unsuitable for further handling and processing. This paper describes the process development for the deposition of 3 μm polysilicon films, achieved with less than one-tenth of wafers broken, through epitaxial low pressure chemical vapor deposition. We found a two-step approach — deposit 2 μm followed by an overlying 1 μm polysilicon film — instrumental in reducing the occurrence of wafer breakage while ensuring the electrical homogeneity of the film.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131973274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}