2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)最新文献

Simulation approach to improving BGA reliability on coreless packages 提高无芯封装BGA可靠性的仿真方法

2012 IEEE 14th Electronics Packaging Technology Conference (EPTC) Pub Date : 2012-12-01 DOI: 10.1109/EPTC.2012.6507164

C. Selvanayagam, Rathin Mandal

{"title":"Simulation approach to improving BGA reliability on coreless packages","authors":"C. Selvanayagam, Rathin Mandal","doi":"10.1109/EPTC.2012.6507164","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507164","url":null,"abstract":"With the increased popularity of ultra-portable electronics such as laptops, microprocessor manufacturers have had to move away from the conventional and highly reliable pin-grid array (PGA) packages and towards ball-grid array (BGA) packages for this market segment due to thickness restrictions. This shift brings with it some reliability concerns. In addition, to shrink the form factor and improve electrical performance further, standard-core substrates are being swapped for thin-core and coreless variations. This work evaluates BGA performance of flip-chip packages with coreless substrates through finite element analysis (FEA) simulation. A three-dimensional quarter-model of a package with no heat spreader on coreless substrate with mixed BGA pitch was used so the location of expected failure can be simulated more accurately. This work then proposes a methodology for improving BGA reliability of coreless packages. Taking into account the behavior of coreless BGA packages, it is proposed that one possible method to improve BGA life in these packages would be to convert the few critical joints to dummy (power/ground plane) joints such that failure of the critical die corner joints does not result in failure of the part. This can be implemented by a design rule that stipulates the replacement of critical die corner joints with dummy joints in coreless substrates. We determined expected percentage improvement in BGA life with the implementation of such a design rule using FEA simulations and Miner's rule: for the BGA layout assumed here, results indicate that 130% improvement in BGA life is possible when five solder joints at the die corner are replaced with dummy joints. This work will be useful for robust design of solder joints in BGA packages with coreless substrates.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124849687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Flux residue cleaning process optimization effect on Flip Chip Ball Grid Array reliability 磁渣清洗工艺优化对倒装球栅阵列可靠性的影响

2012 IEEE 14th Electronics Packaging Technology Conference (EPTC) Pub Date : 2012-12-01 DOI: 10.1109/EPTC.2012.6507154

Y. B. Kar, Noor Azrma Tahk, Foong Chee Seng, L. H. Yang, R. Vithyacharan, T. Yong

{"title":"Flux residue cleaning process optimization effect on Flip Chip Ball Grid Array reliability","authors":"Y. B. Kar, Noor Azrma Tahk, Foong Chee Seng, L. H. Yang, R. Vithyacharan, T. Yong","doi":"10.1109/EPTC.2012.6507154","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507154","url":null,"abstract":"This paper discusses the evaluation and characterizations of the cleaning the organic residues on Flip Chip Ceramic Ball Grid Array (FCCBGA) package. Flux used for Control Collapse Chip Connection (C4) die attachment during assemblies could remain on the die surface as organic residues, thus affecting the integrated circuit performance. Therefore, the effect of implementation flux-cleaning process on the die cleanliness was evaluated. Design of Experiments (DOE) for cleaning chemical parameters using water-based solvents was carried out to investigate the flux-cleaning efficiency. The response for the experiments conducted was die surface cleanliness. The presence and levels of contaminations would be analyzed and characterized using Scanning Electron Microscope (SEM), Fourier Transform Infrared Spectroscopy (FTIR) and Ion chromatography (IC). The optimization process required the integration between mechanical and chemical parameters. Chemical cleaning parameters optimization was aided with Micro Phase Cleaning (MPC) as solvent. Wash temperature and solvent concentration were varied to find the optimal cleaning. Whilst for mechanical parameters, washing pressure, and nozzle orientation are the expected parameters that would give impact to the cleaning process. From the experiments, the cleaning process is optimized with 3% of MPC solvent added into the pure DI water with longer wash exposure time 0.3 m/mm at 10 Psi with 75°C. The optimization result is proven with thermal cycle testing where no delammation or voids are detected even after 2500x.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114916893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Wire bonding capillary vibration behaviour through Laser Doppler Vibrometry & its effects on wire bonding responses 激光多普勒测振法研究金属丝键合毛细管振动特性及其对金属丝键合响应的影响

2012 IEEE 14th Electronics Packaging Technology Conference (EPTC) Pub Date : 2012-12-01 DOI: 10.1109/EPTC.2012.6507088

O. Ho, C. Wee

{"title":"Wire bonding capillary vibration behaviour through Laser Doppler Vibrometry & its effects on wire bonding responses","authors":"O. Ho, C. Wee","doi":"10.1109/EPTC.2012.6507088","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507088","url":null,"abstract":"Ultrasonic vibration behavior of wire bonding capillaries was studied with laser vibrometer at free air and bonding stage. Vibration displacement was measured at transducer, capillary body and capillary tip at the interval of 1mm with Laser Doppler Vibrometer (LDV). This study focus on five different capillaries with same tip design, namely of three standard design capillaries with different main taper angle (MTA) and two special body cut capillaries. Wire bonding responses and capillary vibration behaviors was studied under different conditions. First, they were compared under same bond power setting. Second, each capillary were calibrated with same tip vibration displacement at free air by changing the bond power. Third same ball shear response was calibrated by adjusting bond power. In general, it is observed that when the vibration nodal position is farther from capillary tip (or higher), larger vibration displacement is generated at capillary tip. For special cut capillaries, capillary B with higher vibration nodal position than capillary A has shown larger tip vibration displacement, and it requires lesser bond power to produce same ball shear response. As for standard design capillary, with larger MTA, the vibration nodal position is lower and smaller tip vibration. Although with smaller tip vibration, it has shown better bonding results. The percentage of tip vibration displacement reduction for larger MTA capillary is lesser, and it requires lesser bond power to produce same ball shear response. From this study, we have understood that special cut capillary have different working principles than standard design capillary. The results of this study have demonstrated an in-depth understanding of the ultrasonic vibration behavior of different bonding capillary body design in both free air and bonding stage; and the impact on the wire bonding responses. Subsequently, this understanding is a step forward to develop the capillary material and design guideline.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116424673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Process development to enable die sorting and 3D IC stacking 工艺开发，使模具分类和3D集成电路堆叠

2012 IEEE 14th Electronics Packaging Technology Conference (EPTC) Pub Date : 2012-12-01 DOI: 10.1109/EPTC.2012.6507098

A. L. Manna, R. Daily, G. Capuz, J. de Vos, K. Rebibis, L. Bogaerts, A. Miller, E. Beyne

引用次数: 1

Through-Silicon Interposer (TSI) co-design optimization for high performance systems 高性能系统的通硅介面(TSI)协同设计优化

2012 IEEE 14th Electronics Packaging Technology Conference (EPTC) Pub Date : 2012-12-01 DOI: 10.1109/EPTC.2012.6507058

J. R. Cubillo, R. Weerasekera, G. Katti, R. Patti

{"title":"Through-Silicon Interposer (TSI) co-design optimization for high performance systems","authors":"J. R. Cubillo, R. Weerasekera, G. Katti, R. Patti","doi":"10.1109/EPTC.2012.6507058","DOIUrl":"https://doi.org/10.1109/EPTC.2012.6507058","url":null,"abstract":"Driven by the internet bandwidth ever increasing demand, modern logic integrated circuits (IC) need to cope for logic to memory (DRAM) data throughput above the Terabit per seconds (Tbps) range [1]. Such logic to DRAM interface is affected by the memory wall bottlenecks like: logic operating at much higher throughput and lower latency than DRAM individual modules, and with limited pin count capability organic packaging solutions leading to system architecture using serialization techniques (at the expense of power dissipation and additional circuit latency). Those bottlenecks cannot be addressed individually and need a more global approach with new packaging solutions, new devices and overall enhanced architecture. We will present in this study a silicon packaging solution that can be optimized to achieve the highest possible throughput between logic and DRAM. First, we will explain the concept of high performance silicon carrier with its key specifications as well as the metrics to be analyzed, and then we will provide design rules guidelines and a methodology to optimize such silicon carrier for the highest possible throughput performance.","PeriodicalId":431312,"journal":{"name":"2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114608439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Copper filling of TSVs for interposer applications 中间体应用的tsv的铜填充

2012 IEEE 14th Electronics Packaging Technology Conference (EPTC) Pub Date : 2012-12-01 DOI: 10.1109/EPTC.2012.6507186

N. Jurgensen, Q. Huynh, G. Engelmann, H. Ngo, O. Ehrmann, K.-D. Lang, A. Uhlig, T. Dretschkow, D. Rohde, O. Worm, C. Jager

引用次数: 3

Biocompatible packaging development for an intracranial microsystem 颅内微系统的生物相容性包装开发

2012 IEEE 14th Electronics Packaging Technology Conference (EPTC) Pub Date : 2012-12-01 DOI: 10.1109/EPTC.2012.6507048

L. Ruiqi, T. E. Lim, Tan Kwan Ling, M. Narducci, S. Tao, Cheng Ming-Yuan

引用次数: 0

Effect of thermomechanical fatigue on drop impact properties of Sn-Ag-Cu lead-free solder joints 热机械疲劳对Sn-Ag-Cu无铅焊点跌落冲击性能的影响

2012 IEEE 14th Electronics Packaging Technology Conference (EPTC) Pub Date : 2012-12-01 DOI: 10.1109/EPTC.2012.6507081

Takayuki Kobayashi, S. Terashima, Masamoto Tanaka

引用次数: 0

Mechanical characterization of wafer level bump-less Cu-Cu bonding 晶圆级无凸点Cu-Cu键合的力学特性

2012 IEEE 14th Electronics Packaging Technology Conference (EPTC) Pub Date : 2012-12-01 DOI: 10.1109/EPTC.2012.6507123

L. Peng, L. Zhang, H.Y. Li, G. Lo, C. Tan

引用次数: 2

Towards efficient and reliable 300mm 3D technology for wide I/O interconnects 面向高效可靠的300mm 3D技术，实现宽I/O互连

2012 IEEE 14th Electronics Packaging Technology Conference (EPTC) Pub Date : 2012-12-01 DOI: 10.1109/EPTC.2012.6507102

P. Coudrain, J. Colonna, C. Aumont, G. Garnier, P. Chausse, R. Segaud, K. Vial, A. Jouve, T. Mourier, T. Magis, P. Besson, L. Gabette, C. Brunet-Manquat, N. Allouti, C. Laviron, S. Chéramy, E. Saugier, J. Pruvost, A. Farcy, N. Hotellier

引用次数: 25