Simulation approach to improving BGA reliability on coreless packages

Abstract

With the increased popularity of ultra-portable electronics such as laptops, microprocessor manufacturers have had to move away from the conventional and highly reliable pin-grid array (PGA) packages and towards ball-grid array (BGA) packages for this market segment due to thickness restrictions. This shift brings with it some reliability concerns. In addition, to shrink the form factor and improve electrical performance further, standard-core substrates are being swapped for thin-core and coreless variations. This work evaluates BGA performance of flip-chip packages with coreless substrates through finite element analysis (FEA) simulation. A three-dimensional quarter-model of a package with no heat spreader on coreless substrate with mixed BGA pitch was used so the location of expected failure can be simulated more accurately. This work then proposes a methodology for improving BGA reliability of coreless packages. Taking into account the behavior of coreless BGA packages, it is proposed that one possible method to improve BGA life in these packages would be to convert the few critical joints to dummy (power/ground plane) joints such that failure of the critical die corner joints does not result in failure of the part. This can be implemented by a design rule that stipulates the replacement of critical die corner joints with dummy joints in coreless substrates. We determined expected percentage improvement in BGA life with the implementation of such a design rule using FEA simulations and Miner's rule: for the BGA layout assumed here, results indicate that 130% improvement in BGA life is possible when five solder joints at the die corner are replaced with dummy joints. This work will be useful for robust design of solder joints in BGA packages with coreless substrates.