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2005 IEEE Conference on Electron Devices and Solid-State Circuits最新文献

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High-speed Multiple-Input Maximum and Minimum Circuits 高速多输入最大和最小电路
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635305
C. Yotingoravong, T. Kamsri, A. Chaikla, V. Riewruja
{"title":"High-speed Multiple-Input Maximum and Minimum Circuits","authors":"C. Yotingoravong, T. Kamsri, A. Chaikla, V. Riewruja","doi":"10.1109/EDSSC.2005.1635305","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635305","url":null,"abstract":"This paper presents the multiple-input maximum and minimum circuits, which operate in the current-mode. The realization methods are suitable for fabrication using CMOS technology. The proposed circuits provide the high operation speed and perform the low-distortion in the transfer characteristics. The performances of the proposed circuits were studied using the PSPICE simulation program. The simulation results show the approval of these circuits that they have adequate basic performances for the real-time systems.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134445988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Low-Power CMOS Folding and Interpolating ADC with a Serial-Parallel Domino Encoder 具有串行并行Domino编码器的低功耗CMOS折叠和插值ADC
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635364
Zhen Liu, S. Jia, Zhongjian Chen, Xing Zhang, L. Ji
{"title":"Low-Power CMOS Folding and Interpolating ADC with a Serial-Parallel Domino Encoder","authors":"Zhen Liu, S. Jia, Zhongjian Chen, Xing Zhang, L. Ji","doi":"10.1109/EDSSC.2005.1635364","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635364","url":null,"abstract":"A 8-bit 200MHz low-power CMOS folding and interpolating analog-to-digital converter is designed. A serial-parallel Domino encoder (SPDE) is presented to reduce power dissipation. A special two-stage interpolation network is adopted to decrease static nonlinearity error. The total power dissipation is merely 80mW at a 5V supply.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128073916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
RF Performance and Scaling Capability of Thin-body GOI and SOI MOSFETs 薄体GOI和SOI mosfet的射频性能和缩放能力
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635212
X. An, Ru Huang, J. Zhuge, Xing Zhang, Yangyuan Wang
{"title":"RF Performance and Scaling Capability of Thin-body GOI and SOI MOSFETs","authors":"X. An, Ru Huang, J. Zhuge, Xing Zhang, Yangyuan Wang","doi":"10.1109/EDSSC.2005.1635212","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635212","url":null,"abstract":"The DC and RF performance of thin body GOI and SOI MOSFETs are investigated through simulation. The GOI devices show higher drive current, comparable or even a little lower leakage current than SOI, which indicates that GOI devices have the advantage of thin body structure. For analog/RF applications, GOI MOSFETs demonstrate high cut-off frequency (FT) and gm/Idsratio. With the gate length further scaling down, the cut-off frequency of GOI devices is much larger than SOI and the advantage of GOI devices over SOI is much more remarkable. The reduction in the supply voltage brings favorable advantages for the FTimprovement of GOI devices. The results suggest that GOI devices exhibit stronger scaling capability than SOI for digital and RF applications, and are more suitable for low-power RF applications.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"749 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132947816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
New Dynamic Threshold MOS Structures for Low-Energy True-Single-Phase-Clocking Circuits 用于低能量真单相时钟电路的新型动态阈值MOS结构
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635298
Keng C. Wu, S. Jia, Zhongjian Chen, Xuewen Gan
{"title":"New Dynamic Threshold MOS Structures for Low-Energy True-Single-Phase-Clocking Circuits","authors":"Keng C. Wu, S. Jia, Zhongjian Chen, Xuewen Gan","doi":"10.1109/EDSSC.2005.1635298","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635298","url":null,"abstract":"Higher speed and better saving of energy at low voltage can be gain simultaneously by adopting the dynamic threshold MOS circuit. In this paper, a new scheme was proposed by combining True Single Phase Clocking (TSPC) Logic with dynamic threshold technique. In this scheme the thresholds of the NMOS logic or PMOS logic change only when these transistors need to be turned on and keeps high threshold when they are shut down. And the scheme uses the charge recovery technique of the substrate to further reduce power. It is capable of operating at 0.8V or even lower. The proposed scheme is shown to be 33.45% faster and has 20.86% energy savings compared to the regular TSPC logic circuits, during HSPICE simulations. And last this scheme was further improved in speed.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132961353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Advanced Germanium MOS Devices and Technology 先进锗MOS器件与技术
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635216
C. O. Chui, K. Saraswat
{"title":"Advanced Germanium MOS Devices and Technology","authors":"C. O. Chui, K. Saraswat","doi":"10.1109/EDSSC.2005.1635216","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635216","url":null,"abstract":"It is believed that below the 65 nm node although the conventional bulk CMOS can be scaled, however, without appreciable performance gains. To continue the scaling of Si CMOS in the sub-65 nm regime, innovative device structures and new mate rials have to be created in order to continue the historic progress in information processing and transmission. One such promising channel material is Ge due to its higher source injection velocity. However, the lack of a sufficiently stable gate dielectric and prior knowledge on doping Ge challenged its MOSFET demonstration. In this paper, we review various advanced Ge MOS device technology on nanoscale gate stack, shallow junction, and low thermal budget integration process, which together have enabled fu nctional metal-gated Ge MOSFETs with high-κ dielectric for the first time.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"241 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124649780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Segmented Digital Pulse Width Modulator with Self-Calibration for Low-Power SMPS 一种用于低功耗SMPS的分段数字自校准脉宽调制器
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635283
O. Trescases, Guowen Wei, W. Ng
{"title":"A Segmented Digital Pulse Width Modulator with Self-Calibration for Low-Power SMPS","authors":"O. Trescases, Guowen Wei, W. Ng","doi":"10.1109/EDSSC.2005.1635283","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635283","url":null,"abstract":"The next-generation, digitally controlled DC-DC converters require a high frequency, high resolution, low power and area efficient digital pulse width modulator (DPWM). This paper introduces a self-calibrated segmented DPWM that uses a delay-locked loop to calibrate adjacent delay segments. An 8-bit prototype designed in a 0.13-μm CMOS process operates at a switching frequency of 11.6 MHz, draws 190μA from a 1.2 V supply and occupies only 0.0075 mm2.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125230743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 49
InA1As/InGaAs Metamorphic High Electron Mobility Transistor with a Liquid Phase Oxidized InA1As as Gate Dielectric 以液相氧化InA1As为栅极介质的InA1As/InGaAs变质高电子迁移率晶体管
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635348
Kai-Lin Lee, Kuan-Wei Lee, Men-Hsi Tsai, P. Sze, M. Houng, Yeong-Her Wang
{"title":"InA1As/InGaAs Metamorphic High Electron Mobility Transistor with a Liquid Phase Oxidized InA1As as Gate Dielectric","authors":"Kai-Lin Lee, Kuan-Wei Lee, Men-Hsi Tsai, P. Sze, M. Houng, Yeong-Her Wang","doi":"10.1109/EDSSC.2005.1635348","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635348","url":null,"abstract":"The In0.52AI0.48As/In0.53Ga0.47As metal-oxide-semiconductor metamorphic high electron mobility transistors (MOS-MHEMTs) with a thin InAlAs native oxide layer are demonstrated. After highly selective gate recessing of InGaAs/InAIAs using citric buffer etchant, the gate dielectric is obtained directly by oxidizing InAlAs layer in a liquid phase solution near room temperature. As compared to its counterpart MHEMT, the fabricated InAlAs/InGaAs MOS-MHEMT exhibits larger gate swing voltage, higher drain-to-source breakdown voltage, and at least 1000% improvement in gate leakage current with the effectively suppressed impact ionization effect.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129118996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Enhancement of Extraction Efficiency in Laser-debonded GaN Light Emitting Diodes 激光脱粘GaN发光二极管萃取效率的提高
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635312
C. Chan, T. Yue, C. Surya, A. Ng, A. Djurišić, F. Scholz, C. Liu, M. Li
{"title":"Enhancement of Extraction Efficiency in Laser-debonded GaN Light Emitting Diodes","authors":"C. Chan, T. Yue, C. Surya, A. Ng, A. Djurišić, F. Scholz, C. Liu, M. Li","doi":"10.1109/EDSSC.2005.1635312","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635312","url":null,"abstract":"We conducted detailed investigations of laser-assisted debonding of GaN-based light emitting diodes (LEDs). The devices were grown by metalorganic chemical vapor deposition (MOCVD) on sapphire substrates. After laser debonding the devices were photo-electrochemically (PEC) etched for the roughening of the debonded surface. The dependence of the luminous intensity of the LEDs as a function of the surface roughness was investigated in detailed. A 60% increase in the luminous intensity was observed. This increase is attributed to the enhancement in photon extraction efficiency.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124566408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Simulation of A Monolithically Integrated CMOS Bioamplifier for EEG Recordings 用于脑电图记录的单片集成CMOS生物放大器的仿真
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635356
Su Xiaohong, Liu Jin-bin, Gu Ming, Pei Weihua, Chen Hongda
{"title":"Simulation of A Monolithically Integrated CMOS Bioamplifier for EEG Recordings","authors":"Su Xiaohong, Liu Jin-bin, Gu Ming, Pei Weihua, Chen Hongda","doi":"10.1109/EDSSC.2005.1635356","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635356","url":null,"abstract":"A monolithically integrated CMOS bioamplifier is presented in this paper for EEG recording applications. The capacitive-coupled circuit input structure is utilized to eliminate the large and random DC offsets existing in the electrode-tissue interface. Diode-connected NMOS transistors with negative voltage between gate and source are candidates for large resistors necessary to the bioamplifier. A passive BEF (Band Eliminator Filter) can reduce 50 Hz noise disturbance strength by more than 60 dB. A novel analysis approach is given to help determine the noise power spectral density. Simulation results show that the two-stage CMOS bioamplifier in a closed-loop capacitive feedback configuration provides an AC in-band gain of 39.6 dB, a DC gain of zero, and an input-referred noise of 87 nVrms integrated from 0.01 Hz to 100 Hz.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122526090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Investigation of RF Performance of Nano-Scale Ultra-Thin-Body Schottky-Barrier MOSFETs Using Monte Carlo Simulation 纳米超薄体肖特基势垒mosfet射频性能的蒙特卡罗模拟研究
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635268
Z. Xia, G. Du, Xiaoyan Liu, Jinfeng Kang, R. Han
{"title":"Investigation of RF Performance of Nano-Scale Ultra-Thin-Body Schottky-Barrier MOSFETs Using Monte Carlo Simulation","authors":"Z. Xia, G. Du, Xiaoyan Liu, Jinfeng Kang, R. Han","doi":"10.1109/EDSSC.2005.1635268","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635268","url":null,"abstract":"A Monte Carlo investigation of the dynamic performance of nano-scale ultra-thin-body (UTB) Schottky-Barrier MOSFETs (SB-MOSFETs) is presented. A thorough account of how the gate voltage and SB barrier height affect the RF performance of UTB SB-MOSFETs is elaborated. The UTB SB-MOSFET offers excellent RF performance with high values of fTand fmax. The peak fTis higher than 600 GHz with SB height ranging from 0.2eV to 0.3eV. It is found that gate voltage has a significant influence on fTand fmaxof UTB SB-MOSFETs whereas the barrier height is of minor importance. However, both gate voltage and SB height affect the gmand gdsobviously. For high performance of UTB SB-MOSFETs, appropriate gate voltage and SB height is of great importance.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115312519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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