Advanced Germanium MOS Devices and Technology

Abstract

It is believed that below the 65 nm node although the conventional bulk CMOS can be scaled, however, without appreciable performance gains. To continue the scaling of Si CMOS in the sub-65 nm regime, innovative device structures and new mate rials have to be created in order to continue the historic progress in information processing and transmission. One such promising channel material is Ge due to its higher source injection velocity. However, the lack of a sufficiently stable gate dielectric and prior knowledge on doping Ge challenged its MOSFET demonstration. In this paper, we review various advanced Ge MOS device technology on nanoscale gate stack, shallow junction, and low thermal budget integration process, which together have enabled fu nctional metal-gated Ge MOSFETs with high-κ dielectric for the first time.