{"title":"一种用于低功耗SMPS的分段数字自校准脉宽调制器","authors":"O. Trescases, Guowen Wei, W. Ng","doi":"10.1109/EDSSC.2005.1635283","DOIUrl":null,"url":null,"abstract":"The next-generation, digitally controlled DC-DC converters require a high frequency, high resolution, low power and area efficient digital pulse width modulator (DPWM). This paper introduces a self-calibrated segmented DPWM that uses a delay-locked loop to calibrate adjacent delay segments. An 8-bit prototype designed in a 0.13-μm CMOS process operates at a switching frequency of 11.6 MHz, draws 190μA from a 1.2 V supply and occupies only 0.0075 mm2.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"49","resultStr":"{\"title\":\"A Segmented Digital Pulse Width Modulator with Self-Calibration for Low-Power SMPS\",\"authors\":\"O. Trescases, Guowen Wei, W. Ng\",\"doi\":\"10.1109/EDSSC.2005.1635283\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The next-generation, digitally controlled DC-DC converters require a high frequency, high resolution, low power and area efficient digital pulse width modulator (DPWM). This paper introduces a self-calibrated segmented DPWM that uses a delay-locked loop to calibrate adjacent delay segments. An 8-bit prototype designed in a 0.13-μm CMOS process operates at a switching frequency of 11.6 MHz, draws 190μA from a 1.2 V supply and occupies only 0.0075 mm2.\",\"PeriodicalId\":429314,\"journal\":{\"name\":\"2005 IEEE Conference on Electron Devices and Solid-State Circuits\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-12-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"49\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 IEEE Conference on Electron Devices and Solid-State Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDSSC.2005.1635283\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2005.1635283","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Segmented Digital Pulse Width Modulator with Self-Calibration for Low-Power SMPS
The next-generation, digitally controlled DC-DC converters require a high frequency, high resolution, low power and area efficient digital pulse width modulator (DPWM). This paper introduces a self-calibrated segmented DPWM that uses a delay-locked loop to calibrate adjacent delay segments. An 8-bit prototype designed in a 0.13-μm CMOS process operates at a switching frequency of 11.6 MHz, draws 190μA from a 1.2 V supply and occupies only 0.0075 mm2.
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