New Dynamic Threshold MOS Structures for Low-Energy True-Single-Phase-Clocking Circuits

Abstract

Higher speed and better saving of energy at low voltage can be gain simultaneously by adopting the dynamic threshold MOS circuit. In this paper, a new scheme was proposed by combining True Single Phase Clocking (TSPC) Logic with dynamic threshold technique. In this scheme the thresholds of the NMOS logic or PMOS logic change only when these transistors need to be turned on and keeps high threshold when they are shut down. And the scheme uses the charge recovery technique of the substrate to further reduce power. It is capable of operating at 0.8V or even lower. The proposed scheme is shown to be 33.45% faster and has 20.86% energy savings compared to the regular TSPC logic circuits, during HSPICE simulations. And last this scheme was further improved in speed.